UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer maty
Observer
224 Views
Registered: ‎06-27-2019

Address assignment can only be done within the address range...

Hello, I'm fairly new to all of this. As far as I understand this project, the Microblaze and Zynq will sharing RAM. For this to work, I believe I need to set the offset address range for both processors to match, however every time I try to change it, I get this error message. Please help.

 

 

pic1.PNG
pic2.PNG
pic3.PNG
0 Kudos
1 Reply
Observer maty
Observer
195 Views
Registered: ‎06-27-2019

Re: Address assignment can only be done within the address range...

Update: I followed this solution, https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Vivado-Block-diagram-not-recognising-full-DDR-Memory-size/td-p/465764 and now in the Address Editor screen it does show processing_system7_0_HP0_DDR_LOWOCM at offset addresss 0x0000_0000, which is what I want. However it won't validate, it does not like being at address 0x0000_0000... No matter how hard I try.

 

This is the error message I am getting in the Tcl Console

 

CRITICAL WARNING: [#UNDEF] Address segment /processing_system7_0/Data/SEG_processing_system7_0_HP0_DDR_LOWOCM with base address : 0x00000000 and high address : 0x3fffffff is out of range for M_AXI_GP0. Valid range for M_AXI_GP0 is 0x40000000 - 0x7fffffff
CRITICAL WARNING: [BD 41-1288] Master segment </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> in </processing_system7_0/Data> at <0x0000_0000 [ 1G ]> is illegal. This address exceeds the base address limitations <0x4000_0000 [ 1G ]> of the interface(s) </processing_system7_0/M_AXI_GP0> through which it is accessed by this address space.
0 Kudos