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Registered: ‎11-21-2013

An IPI bug aggregating parametric bus width with $clog2()



I believe there is a bug in the IPI / IP Packager somewhere. We are on VIVADO 2016.4 still, Linux x64.


The test case is very simple and easy to reproduce - we are running a video 720 rows by 1920 columns, and we are creating an AXIS TUSER field based off the following relationship:


output logic [$clog2(C_ROWS) + $clog2(C_COLUMNS):0] m_axis_data;


Basically, we are using bit [0] as frame sync, kinda as recommended by the standard, and the rest of the TUSER field is intended to be used for the row/col video coordinates i.e.


assign m_axis_tdata = {row_cnt , col_cnt , fsync};


The width of the bus should be 22 bits (and ModelSim correctly sets this in the simulation), but the in the project's canvas, it shows as 21 bits wide on the canvas.


The IPI customization Size Left shows 20 and Size Left Dependancy shows:


(spirit:log(2,C_ROWS) + spirit:log(2,C_COLUMNS))


Which is correct, but it should result in 22-bit bus, and not 21-bit.


So that's pretty much it - please let me know if there is a need for further info, but this is definitely an  IPI bug. I may try 2017.1 later today in case this bug has been already addressed.


Thanks you Xilinx.


Vladislav Muravin
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