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Adventurer
Adventurer
3,790 Views
Registered: ‎03-01-2010

Assigning pins affect performance or delays?

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I'm new to the forums and have been working with CPLDs for a couple weeks now.  I've successfully hooked up and programmed a XC9572, using Xylinx software, by schematic entry for a simple adress decoding circuit. I just now learned how to assign pins, which is important because I am close to wiring the circuit up and I don't want small schematic changes to change the pin assignments.

 

My question is: for easier wiring, I'd like to put all the data pins, address pins, etc next to each other so it'll be easier to wire and for equal length data paths. Will this affect the performance of the XC9572 in some way?

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Explorer
Explorer
4,447 Views
Registered: ‎02-27-2010

Re: Assigning pins affect performance or delays?

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I hesitated on replying initially becasue it's been a few years since I worked with the CPLD family.

 

My belief from looking at http://www.xilinx.com/support/documentation/data_sheets/DS063.pdf for the XC9500 Architecture diagram on page 3, the Fast CONNECT Switch Matrix on page 10, and the I/O block starting on page 11, it appears your macrocell goes to wherever you may assign your pin.  The inputs to that macrocell and the feedbacks from other macrocells without any skew in delay.  The only thing that would impact you is if you needed too many inputs to a single function block or if you needed to borrow terms from adjacent macrocells that aren't available due to other placement constraints.  I would think both caveat situations are rather rare.

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2 Replies
Explorer
Explorer
4,448 Views
Registered: ‎02-27-2010

Re: Assigning pins affect performance or delays?

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I hesitated on replying initially becasue it's been a few years since I worked with the CPLD family.

 

My belief from looking at http://www.xilinx.com/support/documentation/data_sheets/DS063.pdf for the XC9500 Architecture diagram on page 3, the Fast CONNECT Switch Matrix on page 10, and the I/O block starting on page 11, it appears your macrocell goes to wherever you may assign your pin.  The inputs to that macrocell and the feedbacks from other macrocells without any skew in delay.  The only thing that would impact you is if you needed too many inputs to a single function block or if you needed to borrow terms from adjacent macrocells that aren't available due to other placement constraints.  I would think both caveat situations are rather rare.

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Adventurer
Adventurer
3,759 Views
Registered: ‎03-01-2010

Re: Assigning pins affect performance or delays?

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Thanks for replying, I really appreciate it. I know I'm a newbie, but I hope to return the favor oneday to someone else... The design I am implementing is fairly simple but I am trying to utilize as many pins as possible. This is my first design, and it is replacing 8 discrete TTL logic IC's. Here's the final resource summary:

 

Macrocells         Product Terms        Function Block             Registers             Pins

Used/Tot            Used/Tot Inps          Used/Tot                      Used/Tot              Used/Tot

16 /72 ( 22%)     30 /360 ( 8%)           45 /144 ( 31%)            11 /72 ( 15%)        33 /34 ( 97%)

 

I think I'll keep the GCK, GTS, and GSR pins assigned from the software the same, and reassign all the other generic I/O. Only 1 pin has been assigned to GCK. Sound good?

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