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Visitor ldm_as
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Registered: ‎09-04-2019

Async Resets for Flops -> what polarity is preferable?

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Hi All,

 

As for the Async Reset for the flops - what polarity is preferable (posedge or negadge)?

 

If I don't define a default value for FF, will it be '0'?

 

Thank you!

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Registered: ‎01-22-2015

Re: Async Resets for Flops -> what polarity is preferable?

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@ldm_as 

In general, Xilinx recommends use of synchronous resets instead of asynchronous resets (see page 76 of UG901(v2019.1)).

A flip-flop with asynchronous clear(reset) is called an FDCE and its primitive is described on page 262 of UG974(v2019.1) for UltraScale devices.  Normally, the CLR(reset) input is active-high. 

Normally, during configuration of the FPGA, the GSR net will assert the CLR input of an FDCE, causing the output, Q, of FDCE to go low (see Xilinx paper WP272).  Usually, we do not rely on the GSR to initialize flip-flops in a design because clocking of the flip-flop can occur after the GSR is released and before our HDL takes control.  However, you will find that the initial output of many flip-flop in your design is unimportant (ie. has no effect on your design).  When the initial output of a flip-flop is important to your design then your design should control the CLR(reset) input to the flip-flop.

Mark

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129 Views
Registered: ‎01-22-2015

Re: Async Resets for Flops -> what polarity is preferable?

Jump to solution

@ldm_as 

In general, Xilinx recommends use of synchronous resets instead of asynchronous resets (see page 76 of UG901(v2019.1)).

A flip-flop with asynchronous clear(reset) is called an FDCE and its primitive is described on page 262 of UG974(v2019.1) for UltraScale devices.  Normally, the CLR(reset) input is active-high. 

Normally, during configuration of the FPGA, the GSR net will assert the CLR input of an FDCE, causing the output, Q, of FDCE to go low (see Xilinx paper WP272).  Usually, we do not rely on the GSR to initialize flip-flops in a design because clocking of the flip-flop can occur after the GSR is released and before our HDL takes control.  However, you will find that the initial output of many flip-flop in your design is unimportant (ie. has no effect on your design).  When the initial output of a flip-flop is important to your design then your design should control the CLR(reset) input to the flip-flop.

Mark