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Visitor pxirouch
Visitor
177 Views
Registered: ‎01-23-2018

Auto infer IP VLNV Interface from System Verilog Interface

Hello,

I am trying to find a way to make vivado packager auto infer the interface of a system verilog module.

The module has the interface declared and instanciated as a SV interface (with modports).

I can do this in verilog by adding the lines:

(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;

But i cant figure out a way to do it in SV where the i/o is declared at the modport..

Is there any way ?

thanks!

 

 

Is there any way (via a directive or macro) , to make Vivado packager auto-infer the Interface when packaging a component

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1 Reply
Moderator
Moderator
68 Views
Registered: ‎03-16-2017

Re: Auto infer IP VLNV Interface from System Verilog Interface

This is IP flows (IPI) related issue hence moving it again to design entry board.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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