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waserin
Visitor
Visitor
584 Views
Registered: ‎07-21-2020

Avoidance of metastable states on FPGA

Hi, all.

 

Conventionally, cascaded two latches/flip-flops are used for avoiding metastable state. But I am wondering if it is alternatively possible to replace the second latch/flip-flop with the LDCE described as below.

Could you please tell me your opinion or advice?

LDCE #(
    .INIT(1'b0)  // Initial value of latch (1'b0 or 1'b1)
) LDCE_inst1b (
    .Q(output_to_my_circuit), // Data output
    .CLR(RESET),               // Asynchronous clear/reset input
    .D(input_from_1st_latch), // Data input
    .G(1'b1),                  // Gate input
    .GE(1'b1)                  // Gate enable input
);

 

I am trying to use this in a part of asynchronous circuits.

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5 Replies
568 Views
Registered: ‎07-23-2019

You won't avoid metastability by using a latch instead of a D-flip flop. The origin of metastability is because data is captured when transitioning, so at an invalid level (not 0, not 1). The difference between a latch and a flip flop is that one captures data with a level, the other with a rising/ falling edge. Because data is asynchronous, you don't know when it will transition, so you can't sync either your edges or your latch capture signals. Same problem.

562 Views
Registered: ‎07-23-2019

You may be thinking that a latch will capture whatever and then somehow you will find when your data is stable then toggle the latch gate to capture data. The problem is because data is asynchronous, it may also change when you toggle the gate and you are screwed up again... there's no way, I'm afraid. Asynchronous data is a problem only solvable if you can foresee the future.

miker
Xilinx Employee
Xilinx Employee
531 Views
Registered: ‎11-30-2007

I would suggest taking advantage of the Xilinx Parameterizable Macros (XPMs) specifically for Clock Domain Crossing (CDC) to mitigate metastability.

forums_xpm_cdc.png

You can find details on the XPM_CDC XPMs in the following documentation:

  • UltraScale Architecture Libraries Guide (UG974; v2020.1; pp 4-31)
  • Vivado Language Templates (Tools > Language Templates)
    • Verilog > Xilinx Parameterizable Macros (XPM) > XPM > XPM_CDC
    • VHDL > Xilinx Parameterizable Macros (XPM) > XPM > XPM_CDC

forums_xpm_cdc_langtemp.png

The XPMs handle the low level properties (i.e. ASYNC_REG) that must be attached to the FFs used to synchronize the signals that cross clock domains.  The presence of the ASYNC_REG attribute on these registers prevents the tool from replicating these registers as well as keeping them physically located together.  You can also reference the following documentation for details:

  • Vivado Design Suite Properties Reference Guide (UG912; v2020.1; pp 143-146)
  • UltraFast Design Methodology Guide for the Vivado Design Suite (UG949; v2020.1; pp 140-144)
    • Chapter 3: Design Creation with RTL > Clock Domain Crossing
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waserin
Visitor
Visitor
427 Views
Registered: ‎07-21-2020

Dear archangel-lightworks,

Thank you for your quick replies.
I’m sorry to hear that it is difficult to solve the metastable state problem in asynchronous circuit, but I would like to continue to find some workaround.

Best regards,
waserin
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waserin
Visitor
Visitor
417 Views
Registered: ‎07-21-2020

Dear miker,

 

Thank you for your suggestion on XPMs and ASYNC_REG.

 The documents you guided told me that there must be a clock signal to use the ASYNC_REG attribute, but I unfortunately have no clock in my circuit.

Actually, the figure below shows my target circuit in which I want to avoid the metastability.

(When I posted here last time, I was going to replace the second quasi-SR-latch with the LDCE.)

 

circuit.png

INA and INB signals change asynchronously, and there are no clocks.

Could you please tell me how to use ASYNC_REG properly in this kind of circuits?
Or if there are any workarounds, could you please let me know about them?

Best regards,
waserin

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