08-19-2020 01:21 PM
I am getting two errors using VIVADO 2020.1 :
[BD 41-237] Bus Interface property FREQ_HZ does not match between /XRNIC_40GbE_0/S00_AXI_0(10000000) and /microblaze_0_axi_periph/m08_couplers/auto_pc/M_AXI(300000000)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /XRNIC_40GbE_0/ACLK_0(10000000) and /ddr4_0/addn_ui_clkout1(300000000)
I cannot attach the design due to FOUO concerns but the gist is an AXI Interconnect ACLK's CONFIG.FREQ_HZ appears stuck at 10,000,000 Hz while
it is being driven by a DDR's user clock @ 300,000,000 Hz.
Does anyone looking at this know how to resolve the issue. It seems I cant change the Interconnect's FREQ_HZ as it is read only.
Happy to give more info if needed but Im hoping someone has run into this type of thing before.
09-14-2020 02:54 AM
Are you sure you connected the correct clock to the correct pin for the interconnect? Maybe try to run validate block design multiple time to make sure the parameters are propagated
10-22-2020 12:46 AM
I often find that there are FREQ_HZ mismatches. It usually happens when I change the output clock frequency from the PS (System Engineers can't decide which frequency is best). In those cases I have to manually change the FREQ_HZ in the .xml and .xci files (I do a text search for FREQ_HZ and then update the values with a text editor).
I would not say that this is a solution, it is only a workaround for this issue that I've found so far.
It doesn't help to clean the project (the .xml and .xci files get deleted... but the FREQ_HZ persists and only updates once those files are modified)
11-05-2020 03:44 PM
Do any of these prior solutions related to that Message # give you any insight?
Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed.