UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Scholar vanmierlo
Scholar
116 Views
Registered: ‎06-10-2008

BUFR doesn't divide properly

Jump to solution

Hi,

I'm not sure if this is the right subforum, but here goes.

I'm using a BUFR to divide an incoming clock by 7, but when I route the input and output clocks out to test pins I can see that sometimes the divided clock (clkdiv) is only 6 periods of the incoming clock (clock_i). But I do not see a glitch on the incoming clock_i to explain this. No need to say that the bits of my ISERDESE2 are slipping.

Here's my topology:

clk_in_p ---|=====\    |========|                 |====|
            |ibufds>---|idelaye2|---clock_i---+---|bufr|---------+-----clkdiv------------>
clk_in_n ---|=====/    |========|             |   |====|         |
| +---|=========| | |=====| |iserdese2| +---|bufio|---clkin----|=========| | |=====| | +------------------------clock_i----------->

Does anyone have an idea how to get to the bottom of this?

Btw. I'm using a Zynq 7010.

Maarten

0 Kudos
1 Solution

Accepted Solutions
Scholar vanmierlo
Scholar
61 Views
Registered: ‎06-10-2008

Re: BUFR doesn't divide properly

Jump to solution

We enabled the terminating resister in the sending ADC and now the clock looks ok.

0 Kudos
2 Replies
Scholar vanmierlo
Scholar
107 Views
Registered: ‎06-10-2008

Re: BUFR doesn't divide properly

Jump to solution

Hmm, using a better oscilloscope I see I do have glitches.

0 Kudos
Scholar vanmierlo
Scholar
62 Views
Registered: ‎06-10-2008

Re: BUFR doesn't divide properly

Jump to solution

We enabled the terminating resister in the sending ADC and now the clock looks ok.

0 Kudos