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Adventurer
Adventurer
8,447 Views
Registered: ‎05-18-2011

Best practices for developing designs with custom IP

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Hello all,

I am developing a Zynq based video processing design using Vivado.  What is the recommended best approach for developing a design that includes Xilinx based IP (such as the Video DMA engine) and custom IP?

I would like to be able to develop and test my IP in isolation with unit test simulation suites that validate the various components that will ultimately be assembled into my video processing chain.  (Think line buffers, and custom processing blocks.)

 

I will also need to generate some other custom IP modules, such as a reset bridge, or perhaps pull in some external logic from the board which have no AXI interface.

 

I have walked through the custom IP creation tutorial (from Avnet's Speedway training) and feel pretty comfortable pressing the appropriate buttons to generate a wrapper for an AXI based peripheral and pulling that into a new design, but what happens when I later need to edit that peripheral?  How do I pull that edited peripheral into my existing design?  Do I need to bump the revision number?

 

I could go on and on with questions like that.  Ultimately, they all boil down to one or two questions...

1) What is Xilinx's recommended best practice or design flow for developing FPGA designs that include custom IP blocks?

 

2) What are other's experience trying to do this?  What works for you?

 

On a related note... the software wenie in me desperately wants to keep as much of the source code as possible (and as little of the generated products) for this design under source code control, and organized in some systematic manner on the file system.  Again, I would hope that recommended best pracitces for doing this would be available somewhere.  Any ideas where I could start looking?

 

Thanks for your help.

 

--wpd

 

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Xilinx Employee
Xilinx Employee
12,564 Views
Registered: ‎09-20-2012

Re: Best practices for developing designs with custom IP

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Hi,

It should be done for every change, else the files in your block design will not be updated.

Thanks,
Deepika.
Thanks,
Deepika.
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Scholar
Scholar
8,436 Views
Registered: ‎09-05-2011

Re: Best practices for developing designs with custom IP

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Adventurer
Adventurer
8,432 Views
Registered: ‎05-18-2011

Re: Best practices for developing designs with custom IP

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Thank you for the resource links.  After a quick perusal, they seem like handy documents to keep handy. :-)

 

They all seem to stop at the "here's how you create you IP" phase.  (Again, I've only briefly scanned them).  I'm also looking for techniques for maintaining, upgrading, bug fixing, etc... my existing IP.

 

Is there some way to tell a Vivado project to reimport an IP block without actually deleting it and adding it again?  I can't find a button to do that.  I have removed an input signal from my IP block and can't figure out how to get it to update in my top level block diagram.  Should I bump the revision number of the IP?  (That makes sense to me -- if the revision number implies a certain revision of the interface, and I change the interface, then I must bump the revision number).  What happens when I simply update the internal implementation without changing the interface.  Should I bump the revision number again?  Or will Vivado automatically pull in the latest version of my HDL?

 

--wpd

 

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Xilinx Employee
Xilinx Employee
8,421 Views
Registered: ‎09-20-2012

Re: Best practices for developing designs with custom IP

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Hi,

 

Is there some way to tell a Vivado project to reimport an IP block without actually deleting it and adding it again?  I can't find a button to do that.  I have removed an input signal from my IP block and can't figure out how to get it to update in my top level block diagram.  Should I bump the revision number of the IP?  (That makes sense to me -- if the revision number implies a certain revision of the interface, and I change the interface, then I must bump the revision number).  What happens when I simply update the internal implementation without changing the interface.  Should I bump the revision number again?  Or will Vivado automatically pull in the latest version of my HDL?

 

When you make changes to the IP (editing HDL/XDC), you need to change the version and re-package it. Later when you do Tools --> Report --> Report IP status in the block design project, it shows that there is a new version of IP available. Now you can upgrade your user IP without removing it.

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Adventurer
Adventurer
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Registered: ‎05-18-2011

Re: Best practices for developing designs with custom IP

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Thank you.  That makes sense.

 

Do I need to bump the revision for every change I make to my IP, or only for those changes that result in a change of the interface (adding or deleting signals)?

 

--wpd

 

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Xilinx Employee
Xilinx Employee
12,565 Views
Registered: ‎09-20-2012

Re: Best practices for developing designs with custom IP

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Hi,

It should be done for every change, else the files in your block design will not be updated.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Xilinx Employee
Xilinx Employee
8,403 Views
Registered: ‎09-20-2012

Re: Best practices for developing designs with custom IP

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Hi,

 

I just rechecked this. Which version of vivado are you using?

 

If you are using vivado 2013.3 or 2013.4 there is no need to change the IP version for the changes to user IP. 

 

After you make changes to the user IP (add or remove signals/ports etc), repackage it (with same version number). In design with BD, refresh the repository and reset BD output products. Now if you generate the output products you can see changes reflected. This was not working correctly in older version of tool which is now fixed.

 

Hope this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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