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fanat91
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Registered: ‎04-21-2020

Bug? Trying to create FIFO READ Master port.

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I'm trying to infer FIFO read master interface like this:

(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 read00 RD_DATA" *) input wire [P_STR_DATA_WIDTH-1:0] INPDATA0;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 read00 RD_EN" *) output wire READEN0;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 read00 EMPTY" *) input wire EMPTY0;

. But when I add my RTL module to block diagram, Vivado generates Slave port and complains about wrong direction for component ports.

WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'INPDATA0' and definition port 'RD_DATA'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'READEN0' and definition port 'RD_EN'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'EMPTY0' and definition port 'EMPTY'.


image.png

Btw, FIFO WRITE Master infers correctly.

A bug or am I missing something?

 

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fanat91
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Registered: ‎04-21-2020

First I'm a bit confused which direction called master/slave. So, I need FIFO read "master".

Second, I added "master" interface ports to your fifo_read.v, first without optional "almost_empty" signal, which I neither have or use in my module:

module fifo_read (
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_SLAVE RD_DATA" *)
  output [15:0] data_slave, // FIFO Read Data (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_SLAVE RD_EN" *)
  input en_slave, // FIFO Read Enable (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_SLAVE EMPTY" *)
  output empty_slave, // FIFO Empty flag (optional)
  
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_MASTER RD_DATA" *)
  input [15:0] data_master, // FIFO Read Data (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_MASTER RD_EN" *)
  output en_master, // FIFO Read Enable (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_MASTER EMPTY" *)
  input empty_master
);

fifo_incorrect.PNG

Then, I decided to try it with "almost_empty" and it worked. See image below. So tool relying on optional signal to determine direction?

fifo_correct.PNG

 

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ashishd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hi @fanat91 ,

It seems there is some mismatch with port direction for some of ports in your interface. Can you please cross check by comparing your interface definition with the one in attached source file? Let me know if you still see warnings with attached file.

Regards,
Ashish
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fanat91
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Registered: ‎04-21-2020

First I'm a bit confused which direction called master/slave. So, I need FIFO read "master".

Second, I added "master" interface ports to your fifo_read.v, first without optional "almost_empty" signal, which I neither have or use in my module:

module fifo_read (
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_SLAVE RD_DATA" *)
  output [15:0] data_slave, // FIFO Read Data (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_SLAVE RD_EN" *)
  input en_slave, // FIFO Read Enable (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_SLAVE EMPTY" *)
  output empty_slave, // FIFO Empty flag (optional)
  
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_MASTER RD_DATA" *)
  input [15:0] data_master, // FIFO Read Data (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_MASTER RD_EN" *)
  output en_master, // FIFO Read Enable (required)
  (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 READ_MASTER EMPTY" *)
  input empty_master
);

fifo_incorrect.PNG

Then, I decided to try it with "almost_empty" and it worked. See image below. So tool relying on optional signal to determine direction?

fifo_correct.PNG

 

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ashishd
Xilinx Employee
Xilinx Employee
297 Views
Registered: ‎02-14-2014

Hi @fanat91 ,

The default directions which are present in language template 'FIFO read interface' are for FIFO slave. Same are present in fifo_read.v file which I've earlier attached. When I tried with FIFO master interface as per your requirement, I can confirm that tool is really relying on optional signals like empty or almost_empty for deciding interface direction which in my opinion isn't correct. This I would say can be an enhancement in interpretation of optional ports by IP Integrator and hence I have reported it through CR. 

Regards,
Ashish
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