12-08-2008 07:22 AM
I posted this in the wrong section, I'm hoping it gets a response here. I'm working on using the CORE generator and wondered if I someone could copy a file in which they add or sub or mult or div floating point numbers using the files generated by the CORE generator. I'm not understanding how to take the files generated and then use them. Sorry if this has been answered before, I tried searching and have tried a lot of searching through google.
12-08-2008 07:31 AM
1. you need to configure the core using COregen.
2. After the core is generated along with the netlist it will genearate a wrapper of VHDL and Verilog.
3. You need to instantiate this wrapper in your top level
Looks an old reference but is useful. http://www.cs.york.ac.uk/rts/docs/Xilinx-datasource-2003-q1/appnotes/xapp410.pdf
12-08-2008 07:56 AM
1 and 2 are done, I took the code from the VHO file and copied into the top level to instantiate.
When I create a test bench waveform I get undefined output though
12-08-2008 08:40 AM
Glad that steps1 and 2 did help.
Can you attach the top level ?
12-08-2008 09:47 AM
Code below, I said output but meant input. The inputs come back red and undefined, even though I specfied them in the TBW. Is this a problem with the instantiation? Ultimately I am converting a matlab program into VHDL for digital engine control. This seems to be the first step necessary and I can't figure this simple thing out.
Solved the error I pm'd you about.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library XilinxCoreLib; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Final_Module is Port ( clk : in STD_LOGIC; a : in STD_LOGIC_VECTOR (31 downto 0); b : in STD_LOGIC_VECTOR (31 downto 0); operation: in STD_LOGIC_VECTOR (5 downto 0); result : inout STD_LOGIC_VECTOR (31 downto 0)); end Final_Module; architecture Behavioral of Final_Module is component AddSubtract port ( a: IN std_logic_VECTOR(31 downto 0); b: IN std_logic_VECTOR(31 downto 0); operation: IN std_logic_VECTOR(5 downto 0); clk: IN std_logic; result: OUT std_logic_VECTOR(31 downto 0)); end component; begin Final_AddSub : AddSubtract port map ( a => a, b => b, operation => operation, clk => clk, result => result); end Behavioral;
12-09-2008 03:19 PM
Am I wrong for thinking I can just view the arithmetic through a test bench waveform?
A proper test bench will know the correct results and compare them to the DUT output, and it will flag any errors.
Of course, you have to actually write such a test bench. Automatically generated test benches are quite limited.