cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
2,126 Views
Registered: ‎07-03-2017

Can Axi4-lite and Axi4 connect with slave?

I have packaged my module to IP with 2 port AXI4-lite Master.

Both of them and another axi4-full port master (from MicroBlaze) are connected with MIG (I believe its an axi4-full slave).

I wonder, Is this possible? Because I didn't find the ID in the AXI4-lite Master interface. And when I do the automated connect the ID (ARID, RID,...)of all of 3 masters connected to ground.

 

Can you help me out of this.

 

Thanks so much.

 

0 Kudos
5 Replies
Highlighted
Scholar
Scholar
2,113 Views
Registered: ‎08-07-2014

Hi,

 

Do you mean you have something like this?

 

               <-- axi4lite --> MIG

Custom IP

               <-- axi4lite --> MIG

 

uBlaze     <-- axi4full --> MIG

 

The MIG core can have only 1 axi i/f. So what about the arbitration if everyone wants to tx/rx data?

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

Highlighted
Observer
Observer
2,100 Views
Registered: ‎07-03-2017

hi @dpaul24,

 

yeah, my block design looks like that.

I thought Axi interconnect will do the arbitration but I do not understand how it works. Can you show me how to set it?

My expect is 2 masters of my custom IP will have the same priority and it's higher than uBlaze.

so if everyone wants to tx/rx data it will be myIP_M00 -> myIP_01 -> uBlaze.

0 Kudos
Highlighted
Scholar
Scholar
2,091 Views
Registered: ‎08-07-2014

Hi,

 

You can use the Xilinx AXI interconnect IP in "N-to-1 AXI Interconnect" mode. The MIG side will be slave side. There is an in-built arbiter.

Read this doc: https://www.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v2_1/pg059-axi-interconnect.pdf

 

See page 12 of the above document.

Excerpt- When multiple master devices arbitrate for access to a single slave device, such as a memory controller, use the AXI Interconnect core in a N-to-1 configuration.

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

Highlighted
Observer
Observer
2,083 Views
Registered: ‎07-03-2017

Hi @dpaul24,

 

Thanks for your help,

I wonder the axi4-lite haven't ID then how can AXI Interconnect determine the transaction belong to whom.

0 Kudos
Highlighted
Scholar
Scholar
2,077 Views
Registered: ‎08-07-2014

Is there any good reason why you are so much focused on ID signals?

 

See page7, "Fixed priority and round-robin arbitration". Choose the one that best fits your design.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos