Can't set PACKAGE_PIN

[swawryk]

I'm using v2014.2 on WinXP for a ZedBoard revD.

I have a design with 3 AXI GPIO blocks using the board presets for LEDs switches and buttons.

I'm now trying to add a 4th AXI GPIO with custom setup rather than a board preset.  After adding it I renamed it "motor_interface", and customized it so that the GPIO is all outputs and 6bits wide, and GPIO2 is all inputs and 2bits wide.

Using connection automation (and I've tried "Create interface port..." with the same result), GPIO is connected to an output port I've renamed "motor_out" and GPIO2 is connected to an output port I've renamed "motor_in".  In the board level constraints I've done "set_property IOSTANDARD LVCMOS33 [get_ports {motor_*[*]}]" and for all of the motor_out/in signals I've located the package pins like, eg: "set_property PACKAGE_PIN AB7 [get_ports {motor_out[0]}]".

"Validate Design" reports no issues, however when I run Synthesis I get a warning and a critical warning for each pin, eg:

[Vivado 12-584] No ports matched 'motor_out[0].'

[Common 17-55] 'set_property' expects at least one object.

What have I missed?

[vuppala · Accepted solution]

Hi,

Try out these steps:

1. Open elaborated design
2. get the ports of the design by running "get_ports" tcl command.

3. Use these port namings to define xdc constraints.

Thanks,
Vinay