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Visitor pa3bgr
Visitor
9,369 Views
Registered: ‎09-10-2014

Clocking wizard does not achieve timing

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dear forum members,

I've run into a problem for I need your help. I have generated the Clocking Wizard IP for my VC707 evaluation board. The wizard takes an external 250 MHz signal as an input and then genreates 750 MHz, 375 MHz, 250 MHz and 125 MHz clock signals. After syntheses, there is a negative slack of 0.214 ns for the 750 MHz clock (1.333 ns). The data sheet specifies a max imum of 933 MHz (VC707 has speed grade -2). So, I am almost 20% below max. How can I achieve timing closure?

Some backgroung info: I am using Vivado 2015.1 and Clocking Wizard v 5.2. All settings are as recommended in PG065: using MMCM, enabled phase alignment, jitter optimization is "balanced", and feedback is "automatic control on-chip". The input clock is LVDS, so I use an IBUFGDS and a BUFG before applying the input clock. 

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Visitor pa3bgr
Visitor
17,048 Views
Registered: ‎09-10-2014

Re: Clocking wizard does not achieve timing

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hi,

The problem has been resolved by removing the phase aligment requirement from the clocking wizard. Apparently, the MMCM can deleiver the frequency, but not in combination with phase alignment. Fortunately I could change my design such that I could accomodate this relaxed requirement. I am glad it works now, but it would have been less stressful if such a relationship was documented better.  (I don't claim it isn't mentioned somewhere, I may have overlooked it)

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Moderator
Moderator
9,365 Views
Registered: ‎01-16-2013

Re: Clocking wizard does not achieve timing

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Hello @pa3bgr,

 

Synthesis timing is only an estimate. Can you try running implementation as it gives exact timing values and check if you still see the timing violations?

 

--Syed

 

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Visitor pa3bgr
Visitor
9,355 Views
Registered: ‎09-10-2014

Re: Clocking wizard does not achieve timing

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that as what i hoped too, but in implementation the setup slack even gets worse.

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Moderator
Moderator
9,352 Views
Registered: ‎01-16-2013

Re: Clocking wizard does not achieve timing

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Hello @pa3bgr,

 

Can you attach the timing report here?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Visitor pa3bgr
Visitor
9,331 Views
Registered: ‎09-10-2014

Re: Clocking wizard does not achieve timing

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Visitor pa3bgr
Visitor
9,325 Views
Registered: ‎09-10-2014

Re: Clocking wizard does not achieve timing

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setup fails (-0.214 ns), see attached. Positive width fails too (-0.075 ns).

Already tried before, all making no difference:

- regenerated IP,

- synthesized OOC with performance-optimized settings, instead of Vivado default settings (in design run window),

- removed manually placed BUFG at input.

timing path.png
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Visitor pa3bgr
Visitor
17,049 Views
Registered: ‎09-10-2014

Re: Clocking wizard does not achieve timing

Jump to solution

hi,

The problem has been resolved by removing the phase aligment requirement from the clocking wizard. Apparently, the MMCM can deleiver the frequency, but not in combination with phase alignment. Fortunately I could change my design such that I could accomodate this relaxed requirement. I am glad it works now, but it would have been less stressful if such a relationship was documented better.  (I don't claim it isn't mentioned somewhere, I may have overlooked it)

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