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Adventurer
Adventurer
5,352 Views
Registered: ‎02-26-2009

Compiling the DDR2 example for the SPartan3AN kit fails with Fatal Error:

Hi,

 

I'm one of these persons, who learn best by beginning from a working starting point and then adapting that setups.

Sonehow providing such simple starting points doesn't really seem to be a strength of Xilinx :-( (or my setup is so special, that everything I try just doesn't work)

 

 

I started with Coregen->MIG to generate a ddr2 controller for the 3AN starter kit.

I wasn't too impressed by the outcome of the tool as already mentioned in http://forums.xilinx.com/xlnx/board/message?board.id=DEENBD&message.id=226#M226  , but alt least I got the file: "sp3a_board_files.zip"

I read the Readme.txt in the top level,  Item "6.)" tells me to go to the par folder and start  "ise_flow.bat", which I did

F:

cd F:\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par

 

Now I get errors and once more I don't know how to proceed:

 

F:\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par>coregen -b ila_coregen.xco
Release 10.1.03 - Xilinx CORE Generator K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
F:\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par/coregen.log
Regenerating IP...
Gathering HDL files for ila root...
Creating XST project for ila...
Creating XST script file for ila...
Creating XST instantiation file for ila...
Running XST for ila...
ERROR:sim - Error: XST failed for ila.
   FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application
   has discovered an exceptional condition from which it cannot recover.
   Process will terminate. For technical support on this issue, please open a
   WebCase with this project attached at http://www.xilinx.com/support.Finished Regenerating.
ERROR:sim:57 - Error found during generation

F:\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par>coregen -b icon_coregen.xco
Release 10.1.03 - Xilinx CORE Generator K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
F:\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par/coregen.log
Regenerating IP...

 

 

 As mentioned above.

I prefer starting with something operational instead of starting from scratch (at least as long as

I am not 100% fluent with the ISE flow.

So I'd really appreciate one (ideally simple)  design forthe 3AN starter kit, that uses the DDR2

controller, and that compiles by simple starting a batch file or a .sh file.

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2 Replies
Xilinx Employee
Xilinx Employee
5,333 Views
Registered: ‎10-23-2007

Re: Compiling the DDR2 example for the SPartan3AN kit fails with Fatal Error:

As a sanity check, I just ran the ise_flow.bat and it went completely through the tools (10.1.3) with no issue.  I did run on a Linux 64 machine (RHEL 4), but I would expect that to run the same as an NT machine for this case.  Possibilities: NT does behave differently or there is something not quite right in your tool installation.  A webcase might be a good idea unless someone else in this forum has other ideas.
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Adventurer
Adventurer
5,330 Views
Registered: ‎02-26-2009

Re: Compiling the DDR2 example for the SPartan3AN kit fails with Fatal Error:

Good idea,

 

I'll try it tomorrow on another WinXP host.

 

I hope, that the problem ccurs on all win-XP hosts, as locating the problem might be really tricky if it is just on my host.

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