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Contributor
Contributor
3,967 Views
Registered: ‎01-04-2017

Create and Package IP

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Hello everyone! I am using vivado 2016.1. I've created block design with IP hierarchies consisting of user and Xilinx Vivado IP, when I package it with the purpose use it to another project I got warnings like:

  • [IP_Flow 19-3153] Bus Interface 'CLK': ASSOCIATED_BUSIF bus parameter is missing.     

After ignoring this warning I paste new IP to the project and I got warnings as bellow:

startgroup
create_bd_cell -type ip -vlnv xilinx.com:user:design_1_wrapper:1.0 design_1_wrapper_0
WARNING: [IP_Flow 19-3571] IP 'fprodsgn_design_1_wrapper_0_0' is restricted:
* IP definition 'design_1_wrapper_v1_0 (1.0)' relies on the following subcore(s) that were not found in the IP Catalog: xilinx.com:user:D_FF:1.0
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.

It is in the list of User IP folder, can I ignore this warning again or help me to solve this problem.

(- I restart the program; - I deleted the existing IP and create over again; - I tried to change the name of IP, but didn't help )

Thanks in advance.

 

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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: Create and Package IP

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you can find more about the ASSOCIATED_BUSIF parameter warning  in UG1118 page 13-14 :

 

"IMPORTANT: The IP Packager checks for the ASSOCIATED_BUSIF parameter for all clock interfaces. The reason for the warning is that the IP integrator tool works best with interfaces, and it was expected that user would typically be using AXI interfaces. If you do not have any bus interfaces in your design, you can safely ignore this warning. For more information on parameters related to clock interfaces, see this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref 17]."

 

so if your custom IP has no bus interface, you can safely ignore it

 

otherwise, you have to associate a clock with your interface, as described here

 

more info about bus interfaces can be found in UG994

 

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7 Replies
Scholar ronnywebers
Scholar
6,101 Views
Registered: ‎10-10-2014

Re: Create and Package IP

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you can find more about the ASSOCIATED_BUSIF parameter warning  in UG1118 page 13-14 :

 

"IMPORTANT: The IP Packager checks for the ASSOCIATED_BUSIF parameter for all clock interfaces. The reason for the warning is that the IP integrator tool works best with interfaces, and it was expected that user would typically be using AXI interfaces. If you do not have any bus interfaces in your design, you can safely ignore this warning. For more information on parameters related to clock interfaces, see this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref 17]."

 

so if your custom IP has no bus interface, you can safely ignore it

 

otherwise, you have to associate a clock with your interface, as described here

 

more info about bus interfaces can be found in UG994

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Create and Package IP

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Hi @marzhan_123,

 

I don't think the 2 warning are related. As mentioned by @ronnywebers, you can specify which clock is associated with your interface.

You should have the option to do it in IP packager for your IP, in the Ports and Interfaces section.

 

You can find a bit more information in UG1118.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
2,797 Views
Registered: ‎01-13-2018

Re: Create and Package IP

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I use the same names for clock and reset signals as mentioned in the tables ( Table 2-2: Reset Signal Naming and Table 2-3: Clock Signal Naming) on page 14 of this document "Creating and Packaging Custom IP 14 UG1118 (v2017.1)" but still there is the same warning "ASSOCIATED_BUSIF bus parameter is missing", please see attachment. 

 

 

 

Untitled23.png
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Scholar ronnywebers
Scholar
2,782 Views
Registered: ‎10-10-2014

Re: Create and Package IP

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@joniengr081, a first remark : I believe you used an active high reset in your code on this post . If I am correct about that, I would use 'rst' or 'reset' instead of 'resetn', because the 'n' is normally used for active low reset signals. It won't make a functional difference if you don't, but it's considered bad coding practice. So fix this first.

 

then to get your warnings fixed, you must add some parameters (read more on this in UG1118, chapter 4 -> adding and removing interface parameters)

 

click on package IP ->  under ports & interfaces you should see something like :

 

ports & interfaces.png

 

right click on the CLK interface (the one marked in blue) -> edit interface -> tab 'parameters'

 

use the '+' to add these 2 parameters.

clock.png

 

@florentw -> I'm not 100% sure if the associated_busif should be set to 'RST', it works for me, but I never 100% understood the meaning of 'associated_busif'.

 

do the same for the 'rst' interface, but with this parameter :

 

reset.png

 

if you don't add this parameter, Vivado will throw warnings when you integrate the IP in a block design and synthesize it. It will tell you that the polarity is not set (or something similar). you can try that out first if you want in a block design, and then add the parameter to see the effect.

 

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Scholar ronnywebers
Scholar
2,776 Views
Registered: ‎10-10-2014

Re: Create and Package IP

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@florentw, just to understand the ports and interfaces better :

 

I've put an AXI GPIO in a block design -> if I right click on s_axi_resetn -> create port, I get this dialog :

 

reset port.png

 

am I correct that this dialog matches with the 'edit interface' dialog in IP packager? So the settings we make in IP packager are reflected here in the 'create port' dialog? So in 'edit interface' in IP packager, we choose or infer 'reset_rtl' as ineterface definition, which corresponds to the 'Type = reset' in the 'create port' dialog above?

 

rst packager.png

 

Same goes for the POLARITY parameter in IP packager, this one matches 'polarity' in the 'create port' dialog?

 

rst polarity.png

 

So the 'create port' dialog is populated with the settings & parameters made in ip packager, but they can still be overruled in the 'create port'  dialog when instantiating the IP on a block diagram?

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Explorer
Explorer
2,767 Views
Registered: ‎01-13-2018

Re: Create and Package IP

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@ronnywebers, I added the properties and it's work. The warnings are removed and I able to package the IP. Thanks !! 

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Moderator
Moderator
2,657 Views
Registered: ‎11-09-2015

Re: Create and Package IP

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Hi @ronnywebers,

 

Yes I think you understanding is correct.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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