cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
9,093 Views
Registered: ‎03-04-2011

DDR

Hi sir,

 

            I has to interface ADC(ADS5282x) and FPGA xilinx board, In FPGA board as iam using a differential signalling (LVds) inputs to the recieving end (FPGA board). In it a DDR interface is needed to the FPGA, for that i have used the DDR block, which takes LCLKp(6xframing clock  with +ve rising edge 'ADCLK') and  LCLKn(6xframing clock  with -ve rising edge 'ADCLK'). My query is, At some point, both signals must be brought into the same clock domain, typically LCLKp. This can be achieved by using register cacade feature using the same IDDR2 primitives as for the standard DDR interface, but with the DDR_ALIGNMENT attribute set to either clock LCLKp or clock LCLKn.In my case i want to set the  DDR_ALIGNMENT attribute to LCLKp. I have written in the following way,(Please see the code which i have inserted with this message) i dont think so it is correct.  Can anyone able to correct it, and can anyone tell me where i was wrong.

                                      Guide me ,Please............

Please reply me as soon as possible,iam awaiting gor your reply.

                                                                       regards

                                                                           shariff.

                                                

 

architecture RTL_Reciever of Reciever is
  signal CH_Q0,CH_Q1:std_logic;

attribute IOB : string;
attribute IOB of <DDR_ALIGNMENT>:signal is "TRUE";  
component IDDR2 
generic  (DDR_ALIGNMENT: std_logic:="None";
            INIT_Q0: std_logic:='0';
            INIT_Q1: std_logic:='0';
            SRTYPE :std_logic:= "SYNC");
  Port
    (D       :in std_logic;
     R       :in std_logic;
     s       :in std_logic;
     C0,C1   :in std_logic;
    Q0,Q1    :out std_logic );    
    
     
end component;  

function RISING_EDGE (signal LCLKp : std_ulogic)
return boolean is

begin
     if (LCLKp'event and LCLKp = '1' and LCLKp'last_value = '0') then
         return true;
     else
         return false;
     end if;
end RISING_EDGE;
begin
  
  IDDR2_OUT : IDDR2
   generic map(
      DDR_ALIGNMENT => "Lclkp",  -- Sets output alignment to "NONE", "C0", "C1" 
      INIT_Q0 => '0', -- Sets initial state of the Q0 output to '0' or '1'
      INIT_Q1 => '0', -- Sets initial state of the Q1 output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map 
      (Q0=> CH_Q0, -- 1-bit output captured with C0 clock  
      Q1=> CH_Q1, -- 1-bit output captured with C1 clock
      C0=> LCLKp, -- 1-bit clock input    -- LCLKp
      C1=> LCLKn, -- 1-bit clock input    -- lCLKn
      CE=> CE,  -- 1-bit clock enable input
      D => RxDat_In,   -- 1-bit data input   -- OUT0p
      R => R,    -- 1-bit reset input --reset
      S => S     -- 1-bit set input   -- '0'
      );
end RTL_Reciever;

 

 

0 Kudos
40 Replies
Highlighted
Teacher
Teacher
9,080 Views
Registered: ‎07-09-2009

what have you tried

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Observer
Observer
9,078 Views
Registered: ‎03-04-2011

I have written the attribute for DDR_alignment and has set it to LCLKp, which was shown in the code. I just want to know whatever i have written, to set the  DDR_alignment attribute to 'LCLKp' is correct or not?

0 Kudos
Highlighted
Teacher
Teacher
9,068 Views
Registered: ‎07-09-2009

does the code synthesise or simulate as you'd expect ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Observer
Observer
9,067 Views
Registered: ‎03-04-2011

No it says, the vhdl compiler existing and points out into the last line i.e. at "end architecture_name;",. What might be the issue?

Q2.Can u please let me know that, whatever i have written DDR_alignment attribute and made it set to (+ve rising clock edge )'Lclkp' is correct way of writting or not? I have searched in many web sites i didnt found exact guidance, what i want.

0 Kudos
Highlighted
Observer
Observer
9,066 Views
Registered: ‎03-04-2011

No it is not simulating.It says the vhdl compiler exiting and points out into the last line i.e. at "end architecture_name;",. What might be the issue?[before i typed it as existing , now i have corrected it, as it shows the vhdl compiler exiting.

0 Kudos
Highlighted
Teacher
Teacher
9,062 Views
Registered: ‎07-09-2009

ok

 

so where is this functino rising_edge from

 

is that not in your normal library ?

 

have you got working code, say a smaller bit ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Observer
Observer
9,058 Views
Registered: ‎03-04-2011

That is declared in the architechture, You can see in the code which i have inserted in my first post. a small template is as given below.

 

function RISING_EDGE (signal LCLKp : std_ulogic)
return boolean is

begin
     if (LCLKp'event and LCLKp = '1' and LCLKp'last_value = '0') then
         return true;
     else
         return false;
     end if;
end RISING_EDGE;

0 Kudos
Highlighted
Instructor
Instructor
9,054 Views
Registered: ‎07-21-2009

I don't know that a function such as RISING_EDGE can be mapped to FPGA hardware.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
9,051 Views
Registered: ‎03-04-2011

I think instead of writing a function for 'Rising edge' Is it better to write as "Lclkp'event", which means whenever recieving clock 'Lclkp' changes i.e. at rising edge or at falling edge then it executes the following statements under if statement, i.e. if(Lclkp'event) then
{
Q<= Rxdatain;
- - - - - - -
-- -- -- -- -- -- - so.on.
}

can i write like that?will it performs as i expected(given in my 1st query).
0 Kudos
Highlighted
Teacher
Teacher
8,908 Views
Registered: ‎07-09-2009

but is rising_edge not already in the lib packages you are calling ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Teacher
Teacher
8,906 Views
Registered: ‎07-09-2009

Ok, 

 

I've looked a bit more 'properly', at your code.

 

dump the rising_edge finction you have written.

     it's not needed.

 

ddr-alignment need to be set to

none, c0 or c1

 

have a read of the data sheet for the ddr as to what none, c0 and c1 mean, I can't rmember, but c0 and c1 are the two clocks into the ddr block.

 

so your instantiation ( part ) could read

 

  IDDR2_OUT : IDDR2
   generic map(
      DDR_ALIGNMENT => "NONE",  -- Sets output alignment to "NONE", "C0", "C1" 
      INIT_Q0 => '0', -- Sets initial state of the Q0 output to '0' or '1'
      INIT_Q1 => '0', -- Sets initial state of the Q1 output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Observer
Observer
8,898 Views
Registered: ‎03-04-2011

Actually, iam bitter puzzeled in writing attribute to the DDr_alignment and that attribute should be set to C0(which is nothing but a +ve edged digital clock and it is 6x times of the framing clock)my doubt is what ever i have written the attribute declaration and specification is correct or not, if not just let me know what is correct one. thank you.
0 Kudos
Highlighted
Teacher
Teacher
8,897 Views
Registered: ‎07-09-2009

hay

 

I'm just a por little engineer just like you.

 

just take out the function you have for rising_edge,

 

and put the instnatiation of the ddr as I have shown,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Instructor
Instructor
8,897 Views
Registered: ‎07-21-2009

For clocking, you have two options:

 

1.  Use ADCLK as input clock source, multiply this clock 12x in a PLL, and clock all the inputs in SDR mode

 

2.  Use LCLK as input source clock, and clock all the inputs in DDR mode

 

For framing:

 

Use ADCLK as a data input, deserialise with ISERDES block, and apply BITSLIP to all inputs until ADCLK (deserialised) is properly word framed (i.e. 12'h03F in each word).

 

There is no need for RISING_EDGE function, from what I can tell.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
8,890 Views
Registered: ‎03-04-2011

thank you for ur reply, I know how to deserialize it and then after it i can store the whole 12 bit data into a 12 bit register, I just want to "in writing attribute to the DDr_alignment and that attribute should be set to C0", how this can be done. tht's it. thank u.
0 Kudos
Highlighted
Instructor
Instructor
8,887 Views
Registered: ‎07-21-2009

I just want to "in writing attribute to the DDr_alignment and that attribute should be set to C0", how this can be done. tht's it. thank u.

That's easy!

From within ISE,

EDIT > Language Templates

In the Language Templates pane,

VHDL > Device Primitive Instantiation > [FPGA family] > I/O Components > DDR Registers

By the way, the "C0" attribute applies to the Spartan-6 ODDR2 primitive, but not the Virtex-5 or Virtex-6 ODDR primitive. If you want to know more about the ODDR attributes, refer to the SelectIO Resources User Guide UG361 for V-6, or FPGA User Guide UG190 for V-5.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
8,880 Views
Registered: ‎03-04-2011

I have written in the following way, as i have read from xilinx templates, which i have attached a file to u.Look on it just tell me is that correct?Will the 'DDR_alignment 'attribute has set to 'C0' or not.If not what is the proper way. 

0 Kudos
Highlighted
Instructor
Instructor
8,877 Views
Registered: ‎07-21-2009

Which FPGA family are you targeting?

 

You cross-posted the exact same topic in the Virtex forum, which suggests you are using Virtex-5 or Virtex-6.

Your code includes the "C0" attribute and you instantiate the IDDR2 primitive, both of which are specific to Spartan devices.

 

So, which FPGA family are you targeting?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
8,869 Views
Registered: ‎03-04-2011

Iam targeting spartan -3E family,(Iam interfacing ADC of TI's to the Xilinx fpga, where i deserialize the serial data transmitted from the TI's ADC.)

                                                  thank u.

0 Kudos
Highlighted
Instructor
Instructor
8,667 Views
Registered: ‎07-21-2009

In the port map, you have the "set" input labeled "s" instead of "S".

 

component IDDR2 
generic  (DDR_ALIGNMENT: std_logic:="None";
            INIT_Q0: std_logic:='0';
            INIT_Q1: std_logic:='0';
            SRTYPE :std_logic:= "SYNC");
  Port
    (D       :in std_logic;
     R       :in std_logic;
     s       :in std_logic;
     C0,C1   :in std_logic;
    Q0,Q1    :out std_logic );

 

If you don't plan on using the set or reset inputs, you should tie them to a constant "0".

 

You have a spelling error in your signal name:

 

signal Qout0,Qout1: std_logic;

attribute IOB : string;                          -- look here is it correct
attribute IOB of <DDR_ALIGNMENT>:signal is "TRUE";
   
   IDDR2_inst : IDDR2
   generic map(
      DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1" -- look here is it correct
      INIT_Q0 => '0', -- Sets initial state of the Q0 output to '0' or '1'
      INIT_Q1 => '0', -- Sets initial state of the Q1 output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q0 => Qout0, -- 1-bit output captured with C0 clock
      Q1 => Qout11, -- 1-bit output captured with C1 clock
      C0 => C0, -- 1-bit clock input
      C1 => C1, -- 1-bit clock input
      CE => CE,  -- 1-bit clock enable input
      D => D,   -- 1-bit data input 
      R => R,    -- 1-bit reset input
      S => S     -- 1-bit set input
   );

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
8,660 Views
Registered: ‎03-04-2011

iam asking one, but your replying differrent please if u have undestood my question, please reply me precisely so that i can understood it, and i can make changes in my code if needed.

thank you.
0 Kudos
Highlighted
Instructor
Instructor
8,652 Views
Registered: ‎07-21-2009

iam asking one, but your replying differrent please if u have undestood my question, please reply me precisely so that i can understood it, and i can make changes in my code if needed.

I am not sufficiently skilled in VHDL to offer you a specific answer to your question.

 

Why not try a synthesis run, and work through any error messages your get until a VHDL wizard stops by to post to this thread.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Teacher
Teacher
8,638 Views
Registered: ‎07-09-2009

hows the home work going ?

 

please remember, we are here as friends, not xilinx employies or your underlings,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Instructor
Instructor
8,636 Views
Registered: ‎07-21-2009

please remember, we are here as friends, not xilinx employies or your underlings,

If I give you my wife's email address, would you be willing to repeat those words?  :)

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
8,629 Views
Registered: ‎03-04-2011

Ok, can u tell me that,when i compiled my code it shows an error indicating "Vhdl compiler exiting" and pointing the cursor to the last line of code i.e. at "end architecture_name;".
0 Kudos
Highlighted
Instructor
Instructor
8,626 Views
Registered: ‎07-21-2009

Ok, can u tell me that,when i compiled my code it shows an error indicating "Vhdl compiler exiting" and pointing the cursor to the last line of code i.e. at "end architecture_name;".

Are you using software other than Xilinx ISE for synthesising your design?

What version of ISE are you using?

What operating system are you running?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Observer
Observer
8,623 Views
Registered: ‎03-04-2011

i am using Modelsim 6.5d for simulation, and windows Xp O.s.
0 Kudos
Highlighted
Observer
Observer
8,618 Views
Registered: ‎03-04-2011

i am using Modelsim 6.5d for simulation, and windows Xp O.s. ....,can u tell me what might be the problem that compiler shows an error indicating "Vhdl compiler exiting" and pointing the cursor to the last line of code i.e. at "end architecture_name;". ....
0 Kudos
Highlighted
Teacher
Teacher
8,618 Views
Registered: ‎07-09-2009

ah the best error of all times,

 

you have an error some where !

 

its great isn't it !

 

So in these situations, divide and conqoure.

  either 

      cut out / comment a large amount of the code, leaving one little bit,

              if that synths, then uncut some of the code, etc.

                   but you need to be caerful to cut the right bits else you get more errors.

 

   or

 

      make small trest code of each bit.

          so put the ddr into into its own architecture,

                see what happens, whebn you have that synthing,

                       vut out another bit, synth that, see what happens.

 

it's either that, or look at the code and get lucky !

 

divide an conqoure.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos