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Registered: ‎11-11-2013

Design flow for vhdl module with multiple instances of multiplier?



I need to generate a VHDL module which receives 2 inputs and returns 1 output, wich results on the computations made over the inputs. The module is defined:


entity mult2_varbitQ is
    Q_a : integer := 2;
    Q_b : integer := 2;
    Q_p : integer := 2
Port (  
    a : in std_logic_vector((Q_a-1) downto 0);
    b : in std_logic_vector((Q_b-1) downto 0);
    p : out std_logic_vector((Q_p-1) downto 0)
end mult2_varbitQ;

Q generics are defined as the number of quantization bits that I am going to use.


Inside the module I need also to instantiate a set of multiplers to perform the operations I want. I am using the simple multiplier present in the IP Catalog. The number of quantization bits shall also be used to configure the input and output bits of the multipliers. I want to make this flexible, having a file with the configuration values like Q and number of multipliers. 


With old ISE (even if it's not the correct way) I would generate, using a external program (using C for instance), the VHDL code to the module, then inside the xilinx project I would generate the multiplier ip and add the auto generated file, using the config file.


With vivado and powerfull TCL I see another option:

I generate the multiplier core using tcl, and use set_property command to change the input bits according to the configuration file. Then, using the Block Design to connect all of my components, I will end up with a block design with my module.


I can also use TCL to generate VHDL code to my module and at the same time to generate the multiplier IP Core that I want to use.


Can you give me some feedback on this subject, about which is the best way to generate a system based on a configuration file, using generics.







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