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8,402 Views
Registered: ‎05-01-2009

Disable block in Vivado block diagram design

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I have several blocks in my design which I would like to disable (not delete) from the design so that my build time is faster. Is there an easy way to do this from the GUI or by editing the hdl that doesn't break the block diagram view? Thanks

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Scholar
Scholar
14,027 Views
Registered: ‎06-05-2013

cepope@nc.rr.com No, There is no way to do this either

-Pratham

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Scholar
Scholar
8,394 Views
Registered: ‎06-05-2013

cepope@nc.rr.com Select the BD you wish to disable and right click disable.

 

shortcut is  ALT + MINUS

 

Through TCL

Example

set_property is_enabled false [get_files design_2.bd]

-Pratham

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Moderator
Moderator
8,389 Views
Registered: ‎01-16-2013

Hi cepope@nc.rr.com,

 

Use the following TCL command:

set_property is_enabled false [get_files  <project_path>/bd/design_2/design_2.bd]

 

In Vivado GUI. Select the block in File hierarchy and right click to Select Disable file as shown below:

 

Capture.PNG

 

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Xilinx Employee
Xilinx Employee
8,380 Views
Registered: ‎09-20-2012

Hi,

 

If you are asking for method to disable IP within block design then there is no such option provided.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Highlighted
8,335 Views
Registered: ‎05-01-2009

Yeah, I see that an entire .bd file can be disabled but I am trying to disable a block within a .bd file leaving the other blocks alone. According to this last answer that isn't possible? Maybe there's a way to export the block(s) I want to disable as .bd files, while keeping the heirarchy, and then disable them? Thanks

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Scholar
Scholar
14,028 Views
Registered: ‎06-05-2013

cepope@nc.rr.com No, There is no way to do this either

-Pratham

----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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Visitor
Visitor
1,440 Views
Registered: ‎01-20-2019

Is there any plan to add this feature in the newer editions?

This seems like it wouldn't be a significant addition and it would help when developing large projects where the synthesis time gets to be stupidly large. Especially when certain elements have issues meeting the timing constraints. 

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Observer
Observer
1,229 Views
Registered: ‎07-02-2018

I would very much like to see this option implemented in Vivado as well.

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Observer
Observer
1,041 Views
Registered: ‎03-21-2019

Disabling rather than deleting a block in a block diagram would be very much like temporarily commenting out a component in VHDL. In VHDL, this is done all the time -- comment this out, comment this in.

This is a feature that is long overdue in IP Integrator.

 

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Adventurer
Adventurer
483 Views
Registered: ‎12-04-2019

Hello

I am also looking for a way to comment out certian portions of the blockdesign. vs having to delete them.

For instance if you have 4 gmii_pcs_pma blocks in the bd, and you want to disconnect one, then being able to comment it out in the bd is more convinent thant haveing to delete it and readd it later. problem with that specific IP is it needs to be tied to external pins otherwise the tool complains. 

 

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