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Participant michaeltymcnamara
Participant
1,086 Views
Registered: ‎07-08-2013

Does the Xilinx IP Packager support Encrypted RTL? (Vivado 2017.4)

I would like to provide an IP for customers to use, which is encrypted, and also packaged.

 

I use the 2017.4 encrypt command to encrypt my IP, and then use the IP packager flow to build a easy to use package that has this IP as a customizable block; but I get the error message from the packager.  The flow works great when I do not use encrypted RTL.  But when I do, the package_project command throws an error.  Is there some option I should change when encrypting IP so that the Vivado IP Packager can handle IP that has been encrypted by the Vivado encrypt command?

 

# create_project -force NAME /my/directory -part xc7z045ffg900-2
# set_property board_part xilinx.com:zc706:part0:1.2 [current_project]
# add_files -norecurse -scan_for_includes S:/my_ip.v
# import_files -norecurse S:/
# update_compile_order -fileset sources_1
# update_compile_order -fileset sim_1
# ipx::package_project -import_files -root_dir S:/ -vendor XXX  -library ip 
No context 'activity' known
Evaluation of 'if' expression failed
ERROR: [Common 17-1392] Control expressions evaluate to unsupported values [S:/myip.v:0]:
bad right evaluation
INFO: [Common 17-206] Exiting Vivado at Thu Aug 16 13:50:32 2018...

 

Below is the logfile of the encryption.  I've tried encrypting the entire file, and also putting the protect block

inside the verilog file, right after the declarations of the input and output ports, and ending the protect block just before the endmodule.  

 

In both cases I get the same error messages:

No context 'activity' known
Evaluation of 'if' expression failed
ERROR: [Common 17-1392] Control expressions evaluate to unsupported values 

 

# encrypt -key ${keyfile} -lang verilog -verbose ${ipsrc}
Parsed 1 envelopes:
94 common:error_handling = "delegated"
95 common:decryption = (activity == simulation) ? "false" : "true"
Key Xilinx::xilinxt_2017_05:
107 :xilinx_configuration_visible = "false"
108 :xilinx_enable_modification = "false"
109 :xilinx_enable_probing = "false"
110 :xilinx_enable_bitstream = "true"
Digest text for envelope at [S:/my_ip.v:90]
control error_handling = "delegated"<
control decryption = (activity==simulation)? "false" : "true"<
rights_digest_method="sha256"<
key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa", key_block<
gDqHvCESOypngWZApKVmuVhfdpH6WB2Xz/63eJs6Q+AO+Ul2/5xE94Y+iWqC8WLxgE+NtOlGtBSS<
raTXN8tPn24SKWRqDLk0On5axv2dKB1Ruydl2FFeGfJj5U2ovyGI9rC7PUPNVNcORFihzYPHBtDs<
7mXmmLMaItSZfjhzJ/mjzmTfxILdPeg37/MCvtmAihQlxsR2bRZAveYJnx29Vo16k44TdqHb3QQp<
jWLa6g5cbB1NA3TgMYrtPIL2SwrdZJncp7KTkOakV3AEkY0Kplk2/ePbkaKrNJI4k2f3kHu0P2qZ<
2UA0f8LTijrcJndhD1cdPwfye/GFJvfALHHQtw==<
control xilinx_configuration_visible = "false"<
control xilinx_enable_modification = "false"<
control xilinx_enable_probing = "false"<
control xilinx_enable_bitstream = "true"<
===
INFO: [Common 17-206] Exiting Vivado at Thu Aug 16 13:50:13 2018...

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3 Replies
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Participant michaeltymcnamara
Participant
1,073 Views
Registered: ‎07-08-2013

Re: Does the Xilinx IP Packager support Encrypted RTL? (Vivado 2017.4)

As further debugging, I tried enabling all of the activities that I could see:

 

`pragma protect control xilinx_configuration_visible = "true"
`pragma protect control xilinx_enable_modification = "true"
`pragma protect control xilinx_enable_probing = "true"
`pragma protect control xilinx_enable_bitstream = "true"

 

but still encrypting, and I get the same error message from the packager.

 

It seems the packager just doesn't know that it should decrypt?

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Participant michaeltymcnamara
Participant
1,038 Views
Registered: ‎07-08-2013

Re: Does the Xilinx IP Packager support Encrypted RTL? (Vivado 2017.4)

I used the Vivado tool to package the IP (rather than my IP packaging scripts which I built from previous uses of the Vivado packager).  This did allow me to get further; but not to the finish line. 

 

I was able to successfully package the IP, but when I use it in the a design, I get:

 

Top: design_wrapper
ERROR: [Common 17-1392] Control expressions evaluate to unsupported values [s:/BB_fpga/vivado/bbp/design_1.srcs/sources_1/bd/design/ipshared/48b0/myip.vp:0]:
bad right evaluation
ERROR: [Synth 8-1769] cannot open verilog file s:/BB_fpga/vivado/bbpdesign_1.srcs/sources_1/bd/design/ipshared/48b0/myip.vp
Failed to read verilog 's:/BB_fpga/vivado/bbp/design_1.srcs/sources_1/bd/design/ipshared/48b0/baseband.vp'

 

The file is indeed at that location, and it is properly encrypted.

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Observer jeanalexisb
Observer
597 Views
Registered: ‎11-01-2017

Re: Does the Xilinx IP Packager support Encrypted RTL? (Vivado 2017.4)

Same issue here.

Any resolution to this case?

Jean-Alexis

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