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5,110 Views
Registered: ‎02-09-2010

Duplicate Design Unit 'base_zynq_ps7_0_axi_periph_0' found in library 'xil_defaultlib'

Dear all,


I have a design with a Zynq under Vivado 2017.2. I have switched to Vivado 2017.4 and upgraded the design (IPs, ...). Now I have always the following warning under Implementation->Design Initialization:
[filemgmt 20-1318] Duplicate Design Unit 'base_zynq_ps7_0_axi_periph_0' found in library 'xil_defaultlib'

I have tried to "reset output products" and "generate output products". It does not help.

My question seems similar to
https://forums.xilinx.com/t5/Vivado-TCL-Community/Duplicate-design-unit-Synthesis-intended-file-conflicting-with/m-p/552804
but it was in 2014...

To be more complete, my original project under Vivado 2017.2 had another warning:
[IP_Flow 19-3664] IP 'base_zynq_processing_system7_0_0' generated file not found '....srcs/sources_1/bd/base_zynq/ip/base_zynq_processing_system7_0_0/stats.txt'. Please regenerate to continue.

 

 PS. The first warning above appear also under "Analysis results" and "Synthesis".

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Xilinx Employee
Xilinx Employee
5,043 Views
Registered: ‎09-20-2012

Hi tcachat@metraware.com

 

Can you try using "OOC per IP" option while generating block design output products?

Thanks,
Deepika.
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5,040 Views
Registered: ‎02-09-2010

I have already tried both "OOC per IP" and "Global" for the block design output products. The result is the same. Now I just tried "OOC per Block Design", and again it is the same.

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Moderator
Moderator
5,025 Views
Registered: ‎11-09-2015

Hi tcachat@metraware.com,

 

This is a bit extreme but could you try to:

  1. close vivado
  2. delete the .cache, .ip_user_files, .ipderfs and .run

And try to re-run synthesis.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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4,991 Views
Registered: ‎02-09-2010

Hi Florent

 

I have completely removed the folders <project>.cache, <project>.p_user_files,and <project>.runs (with S)

I had no folder <project>.ipderf

But the warning is still there, before and after synthesis. I tried another time to remove the folders and force "generate output products", but the warning is still there.

 

I do not know whether it is related: under the "Design Runs" tab, under "Out-of_Context Modules Runs"->base_zynq I always read "Using cached IP results" (even after removing the folders).

 

Thank you

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Moderator
Moderator
4,986 Views
Registered: ‎11-09-2015

Hi tcachat@metraware.com,

 

Could you share a test case? It might help to undestand what is going wrong.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Highlighted
4,850 Views
Registered: ‎02-09-2010

Sorry for the delay.


Steps to reproduce:

 

  • In Vivado 2017.2 "Open Example Project", chose "Base Zynq", "ZC702 eval".
  • "Generate Output Products"
  • "Generate Bitstream"
  • Close the project, then open it with Vivado 2017.4 and accept the following proposed actions:
  • "automatically upgrade"
  • "Report IP status"
  • clic "upgrade selected"
  • "Generate output products"
  • wait (it is not clear to me whether I should have waited before "Generate output products")
  • run synthesis/implementation

 

I tried to attach a zip of my project, but it was too big (and the error message only appeared after I manually stop the never ending transfer).

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4,846 Views
Registered: ‎02-09-2010

You can also download my project at http://dl.free.fr/j5pnDsI6Q

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Observer
Observer
4,833 Views
Registered: ‎05-30-2014

Hi,

 

I have the same effect after porting a project from 2017.2 to 2017.4.

Directly after opening the project the warning messages appear under Analysis Results/sources_1 and /sim_1:

  • [filemgmt 20-1318] Duplicate Design Unit 'ZCU102_PoC_axi_interconnect_0_0' found in library 'xil_defaultlib'

I had another "Duplicate" warnings because some files where indead in the folder /sources_1/bd/../hdl and also in .../synth.

I guess that 2017.2  used /hdl and 2017.4 now /synth. I just deleted the older versions out of /hdl.

 

Probably this xil_defaultlib is also such an incompatibility ... but I also couldn't found the cause.

 

The project is nevertheless compilable with working results ...

 

Marc

 

P.S. What I'm currently fighting with is the hardware export to the SDK. The SDK is not recognizing newly added AXI components and still thinks to work with 2017.2 ...The .hdf is new generated and also the system.hdf in the SDK (but with an old date and with the old 2017.2 version in it) !?!?!??

 

 

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Moderator
Moderator
4,710 Views
Registered: ‎11-09-2015

Hi tcachat@metraware.com,

 

Sorry about the delay.

 

It just seems that the IPs have change and in 2017.4, the sub-ip axi_periph is not needed anymore.

 

If you remove it from .srcs/source_1/bd/base_zynq_ip, you won't have the warning anymore:

zynq.PNG

 

The reason is because in 2017.4, the axi_periph is now part of the RTL code generated under the BD and not a separated IP anymore.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Highlighted
3,253 Views
Registered: ‎02-09-2010

Thank you, it works.

Sorry it works not really. When I remove the whole folder, the warning disappear, but as soon as I compile the design, the folder and the warning reappear. It seems to work if I remove the bloc from the Bloc Design, and replace it by a new bloc.

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Moderator
Moderator
3,231 Views
Registered: ‎11-09-2015

Hi tcachat@metraware.com,

 

Thanks for sharing your workaround.

 

Note that the warning can be ignored.

 

Another solution can be to use write_bd_tcl to generate a tcl file for the bd and then rebuild the bd.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
Observer
1,542 Views
Registered: ‎06-12-2018

Hi tcachat,

which block did you replace? Axi Interconnect?

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