01-11-2018 06:29 AM - edited 01-12-2018 12:46 AM
I have a design with a Zynq under Vivado 2017.2. I have switched to Vivado 2017.4 and upgraded the design (IPs, ...). Now I have always the following warning under Implementation->Design Initialization:
[filemgmt 20-1318] Duplicate Design Unit 'base_zynq_ps7_0_axi_periph_0' found in library 'xil_defaultlib'
I have tried to "reset output products" and "generate output products". It does not help.
My question seems similar to
but it was in 2014...
To be more complete, my original project under Vivado 2017.2 had another warning:
[IP_Flow 19-3664] IP 'base_zynq_processing_system7_0_0' generated file not found '....srcs/sources_1/bd/base_zynq/ip/base_zynq_processing_system7_0_0/stats.txt'. Please regenerate to continue.
PS. The first warning above appear also under "Analysis results" and "Synthesis".
01-12-2018 12:47 AM
Can you try using "OOC per IP" option while generating block design output products?
01-12-2018 01:00 AM
I have already tried both "OOC per IP" and "Global" for the block design output products. The result is the same. Now I just tried "OOC per Block Design", and again it is the same.
01-12-2018 08:38 AM
This is a bit extreme but could you try to:
And try to re-run synthesis.
01-15-2018 04:27 AM
I have completely removed the folders <project>.cache, <project>.p_user_files,and <project>.runs (with S)
I had no folder <project>.ipderf
But the warning is still there, before and after synthesis. I tried another time to remove the folders and force "generate output products", but the warning is still there.
I do not know whether it is related: under the "Design Runs" tab, under "Out-of_Context Modules Runs"->base_zynq I always read "Using cached IP results" (even after removing the folders).
01-15-2018 05:15 AM
Could you share a test case? It might help to undestand what is going wrong.
01-30-2018 08:44 AM
Sorry for the delay.
Steps to reproduce:
I tried to attach a zip of my project, but it was too big (and the error message only appeared after I manually stop the never ending transfer).
01-30-2018 09:29 AM
01-31-2018 01:57 AM
I have the same effect after porting a project from 2017.2 to 2017.4.
Directly after opening the project the warning messages appear under Analysis Results/sources_1 and /sim_1:
I had another "Duplicate" warnings because some files where indead in the folder /sources_1/bd/../hdl and also in .../synth.
I guess that 2017.2 used /hdl and 2017.4 now /synth. I just deleted the older versions out of /hdl.
Probably this xil_defaultlib is also such an incompatibility ... but I also couldn't found the cause.
The project is nevertheless compilable with working results ...
P.S. What I'm currently fighting with is the hardware export to the SDK. The SDK is not recognizing newly added AXI components and still thinks to work with 2017.2 ...The .hdf is new generated and also the system.hdf in the SDK (but with an old date and with the old 2017.2 version in it) !?!?!??
02-09-2018 06:47 AM
Sorry about the delay.
It just seems that the IPs have change and in 2017.4, the sub-ip axi_periph is not needed anymore.
If you remove it from .srcs/source_1/bd/base_zynq_ip, you won't have the warning anymore:
The reason is because in 2017.4, the axi_periph is now part of the RTL code generated under the BD and not a separated IP anymore.
02-09-2018 08:29 AM - edited 02-09-2018 09:34 AM
Thank you, it works.
Sorry it works not really. When I remove the whole folder, the warning disappear, but as soon as I compile the design, the folder and the warning reappear. It seems to work if I remove the bloc from the Bloc Design, and replace it by a new bloc.
02-12-2018 01:16 AM - edited 02-12-2018 01:16 AM
Thanks for sharing your workaround.
Note that the warning can be ignored.
Another solution can be to use write_bd_tcl to generate a tcl file for the bd and then rebuild the bd.
07-10-2019 03:29 AM
which block did you replace? Axi Interconnect?