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Adventurer
Adventurer
3,132 Views
Registered: ‎12-16-2010

EDIF netlist and external blocks

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Hello,

I'm trying to use an EDIF netlist in Vivado.

The EDIF file uses some logic blocks which are included as "external" and declared / implemented in another file.

The EDIF module is included in a third top module.

 

This is the hierarchy:

 

top_module.vhd

    processing.edif

          hal.vhd

 

The EDIF module uses some modules declared and implemented in hal.vhd.

In processing.edif file, these's a directive referring to external hal.vhd file:

 

  (external work

    (edifLevel 0)
    (technology (numberDefinition))
    (cell RAM_WRAPPER

 

and in hal.vhd file:

 

entity RAM_WRAPPER is

   ...

end RAM_WRAPPER;

 

 

The synthesis works, but implementation gives this error:

 

 [Project 1-486] Could not resolve non-primitive black box cell 'RAM_WRAPPER' instantiated as 'inst_top_module/inst_RAM_WRAPPER'

 

Implementation is not finding the required sub-block for the EDIF module.

Probably there's some error with the name of the library "exported" by hal.vhd and the library name "imported" by processing.edif.

How could I fix this problem?

 

Thanks

Andrea

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1 Solution

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Adventurer
Adventurer
1,699 Views
Registered: ‎12-16-2010

Re: EDIF netlist and external blocks

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So, as I'm trying to use a vhd in place of edif file, the answer is that you can't...

 

Thanks

Andrea

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7 Replies
Moderator
Moderator
3,127 Views
Registered: ‎01-16-2013

Re: EDIF netlist and external blocks

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@andpas,


Can you please share a test case to reproduce the issue?

For such errors, my first debug step would be to check if all the files are correctly added to the Vivado project.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
3,065 Views
Registered: ‎07-01-2015

Re: EDIF netlist and external blocks

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Hi @andpas,

 

  1. Can you please try with Post-synthesis project in case you are using RTL project?
  2. Is the EDIF file name matching the top module name in the EDIF file?
  3. Can you please share the complete steps you are using?
Thanks,
Arpan
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Adventurer
Adventurer
2,996 Views
Registered: ‎12-16-2010

Re: EDIF netlist and external blocks

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Hello,

unfortunately I can't supply a project, as it contains protected IPs.

 

The fact is, from my tests, if you add to the project an EDIF referencing to external entities, these entities will work only if they are included in other EDIF too.

If the nested entities are added as VHDL, they are simply ignored.

But if you synthesize the VHDL to EDIF, then you add the EDIF to the project, it will work, but of course it's not very comfortable if you need to change generic parameters on the nested code.

 

I suppose it's a question of library names...

Any help from the Xilinx technical support?

 

Thanks

Andrea

 

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Contributor
Contributor
1,342 Views
Registered: ‎10-01-2014

Re: EDIF netlist and external blocks

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I have similar problem. I have a top edf source file but other .edn files are not showing as sub-hierarchical blocks of this main entity. How can I solve this?

 

Please have a look into:

 

8.PNG

 

For example: IQ_TX_c_addsub... should be under IQ_TX.edf

 

Looking for hearing from you,

 

Regards,

 

Rodolfo

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Xilinx Employee
Xilinx Employee
1,334 Views
Registered: ‎05-08-2012

Re: EDIF netlist and external blocks

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Hi @andpas. The hal.vhd should be added as another EDIF file, since it is contained within an EDIF. I would also suggest changing the compile order of the implementation to manual based on the following answer record.

 

https://www.xilinx.com/support/answers/63121.html

 

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Moderator
Moderator
1,287 Views
Registered: ‎06-14-2010

Re: EDIF netlist and external blocks

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Hello @andpas,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

 

If this is not solved/answered, please reply in the thread.

 

Thanks in advance and have a great day.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Adventurer
Adventurer
1,700 Views
Registered: ‎12-16-2010

Re: EDIF netlist and external blocks

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So, as I'm trying to use a vhd in place of edif file, the answer is that you can't...

 

Thanks

Andrea

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