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08-22-2013 05:03 PM
I am doing a Aurora 8B/10B design using the version 8.3 Aurora core in CoreGen. I am targeting a Spartan-6 150T part. When I do a syntax check of the example design, I get the following error message: "ERROR:HDLCompiler:104 - Cannot find <aurora_pkg> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file." This is true since CoreGen generates a file named "Aurora_720p_Transceiver_aurora_pkg" appending my design name to the front of "aurora_pkg." However, when I change the file name called out by CoreGen to "Aurora_720p_Transceiver_aurora_pkg", and add that file to the project, I still get the same error.
This error occurs in the top level file for the example design. Why is the error not corrected by supplying the correct file name?
08-23-2013 10:41 AM
I checked the "Include as Global File in Compile List" box and still get the same error. I then took a closer look at the package source file and found the package and body names were the default names supplied by CoreGen. I appended the component name to the front of the default name and that solved the problem.
It would be nice if this was mentioned in the Xilinx documentation. Perhaps I missed it, but I picked up from the documentation that you only need to modify the top file out of CoreGen, but you actually need to go down into the output hierarchy and modify some of the other files. So far I have only done a syntax check. I am about to synthesis the design and go into PlanAhead to assign pins. Are there any other similar potholes in the road ahead as I go into simulation, etc?
Thanks for the suggestion. It pushed me toward the solution.
08-22-2013 06:58 PM
Does it work if you set aurora_720p_transceiver_aurora_pkg.vhd as global included?
Vivian
08-23-2013 10:41 AM
I checked the "Include as Global File in Compile List" box and still get the same error. I then took a closer look at the package source file and found the package and body names were the default names supplied by CoreGen. I appended the component name to the front of the default name and that solved the problem.
It would be nice if this was mentioned in the Xilinx documentation. Perhaps I missed it, but I picked up from the documentation that you only need to modify the top file out of CoreGen, but you actually need to go down into the output hierarchy and modify some of the other files. So far I have only done a syntax check. I am about to synthesis the design and go into PlanAhead to assign pins. Are there any other similar potholes in the road ahead as I go into simulation, etc?
Thanks for the suggestion. It pushed me toward the solution.
08-25-2013 07:30 PM
I wonder if the original key problem of this issue is not the name of the file but the file not being added into project sources. Does it work if you do not change the file name and the package and body names in it but just add it into project sources?
Vivian
08-26-2013 10:26 AM
Yes, the syntax check passes with no errors or warning after restoring the original file, package, and body names, and performing a Project File Cleanup. Is it correct to assume that CoreGen should have added this file to the generated project?