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Observer legoman
Observer
134 Views
Registered: ‎06-14-2012

Editing Xilinx IPs

I know that it is possible to edit lower levels of Xilinx IPs with following method:

Vivado 2016.3 and Newer:
1. Clear IP cache. Tools > Project Settings > IP > Clear Cache.
- Skip if new IP and/or design.
2. Generate RTL using the following TCL command.
- generate_target all [get_files /ip_location/ip_name/ip_name.xci]
3. Modify the RTL in your preferred text editor outside of Vivado
4. Generate ip_user_files using the following tcl command.
- export_ip_user_files -of_objects [get_files /ip_location /ip_name/ip_name.xci] -no_script -sync -force -quiet
5. Create and OOC run for the IP using the following TCL command.
- create_ip_run [get_files -of_objects [get_fileset sources_1] /ip_location/ip_name/ip_name.xci]
6. Run synthesis on the OOC run.
- launch_runs -jobs 4 ip_name_synth_1

But is it possible to add custom input and output ports to already existing Xilinx IP? Seems that outputs those I add to modified top level of the IP are not recogniced by Vivado.

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2 Replies
Moderator
Moderator
130 Views
Registered: ‎11-04-2010

Re: Editing Xilinx IPs

Hi, @legoman ,

Hope the AR-57546 can be helpful.

https://www.xilinx.com/support/answers/57546.html

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Observer legoman
Observer
81 Views
Registered: ‎06-14-2012

Re: Editing Xilinx IPs

Solved this by deleting the IP core cache and runs before launching the new run.

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