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rs2015
Participant
Participant
7,669 Views
Registered: ‎09-17-2014

Editing a custom bus interface

I know how to create a custom bus interface in Vivado (Tools -> Create Interface Definition)

 

However, I would like to modify a bus interface that I created.  Is there a way to do this?  (other can editing the xml files directly)

 

Thanks

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6 Replies
rs2015
Participant
Participant
7,668 Views
Registered: ‎09-17-2014

*other THAN editing the xml files directly

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apfelsaft
Visitor
Visitor
6,125 Views
Registered: ‎11-19-2015

Same question, no solution yet?

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ronnywebers
Advisor
Advisor
4,389 Views
Registered: ‎10-10-2014

no don't edit manually ... editing an existing bus interface is indeed a bit like a 'hidden feature' - I've searched a while myself.

 

I've found 2 ways :

 

1) easiest : Vivado -> menu 'File' -> Open IP XACT file -> browse to either of the 2 xml files

2) or via IP catalog (if you haven't added the interface definition to your catalog, then do this first). Then on the top window, next to 'cores' click on 'interfaces' tab ->  search for your interface, probably under 'users' -> right click -> edit interface

 

Note that UG1118 chapter 5 mentions the first method.

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embedded
Advisor
Advisor
679 Views
Registered: ‎06-09-2011

Hi @ronnywebers ,

I know this post dates back to three or more years ago. However, I am wondering what would be the usage of "create interface definition" feature in Vivado. Whether we can create an IP which has ports like this? How could this be possible?

I would really appreciate your help.

 

Thanks,
Hossein
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ronnywebers
Advisor
Advisor
670 Views
Registered: ‎10-10-2014

@embedded hope I understand your question correctly - so I think you want to know when custom interfaces can be useful? 

so first of all, Interface definitions are just groupings of signals, which reduce clutter in the block designs. On top of that, for each signal in the interface, you can define some properties, i.e. wether it's a clock, a data line, a data bus, the direction, wether it's required or not, .... If you follow certain rules in the naming of signals, Vivado can even 'deduct' from the name wether it's a clock, or a reset signal. These definitions help you to avoid mistakes, as Vivado will do some DRC's (Design Rule Checks) automatically for you on the connections that you make with the interface definition. 

For all details I'd like to refer to UG1118 (i.e. chapter 2 explains the inferring of signals, chapter 5 explains all the details if you want to create your own interfaces. But I would just read through the complete manual if you want to start creating your own interfaces, or if you want to better understand how the IP designer connections work.

then about your question : yes I think the most common use case is when you want to add an interface to your own custom IP, to group signals, so you only have to draw one (big fat) line in the block design to connect with another (probably also custom) IP having the same interface. I don't see any real other use case here, but I might be missing something.

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embedded
Advisor
Advisor
656 Views
Registered: ‎06-09-2011

Hi @ronnywebers ,

First, thank you for your prompt answer. Yes, I wanted to know the usage of this interface design and how to use it in my own IP package. Because I want to create a custom AXIS_Through IP to use it for connecting two Xilinx IP cores in a little bit strange way. In my application, I have an AXIS_switch connected to AXIS_dwidth_converter IP. I have crossed tid and tuser of these two blocks - switch output as master and dwidth_converter as slave. I just wanted to create a custom IP that I can do this crossing inside an RTL code. My problem is that - I read about inferring of signals and tried to follow those rules - I created my custom IP - let's name it AxisCross -but I can't - for example - connect AxisCross master to dwidth_converter slave or AxisCross slave to switch master. As soon as i take the pencil in the canvas toward those ports I see the small box shows up indicating that "No matching connection found for M0_AXIS". However, if I create an AXI IP from the wizard they can be connected - the problem of this AXIS is that it lacks of tid and tuser pins. I have also another question that I can't figure it out the question mark on those two pins in the below picture:

MyCore.png

I really appreciate your help.

Thanks,
Hossein
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