08-28-2019 05:57 AM
I tried to implement Zynq UltraScale＋ MPSoC VCU TRD 2018.3 - SDI Video Capture and SDI Display project. I generated bitstream and exported it but when I try to run the these commands, I got an error in the 3rd one:
set_param dsa.writeHDFData 1
set_property dsa.name vcu_sdirxtx [current_project]
write_dsa -unified -force ./vcu_sdirxtx.dsa
INFO: [Vivado 12-4895] Creating DSA: ./vcu_sdirxtx.dsa ...
ERROR: [Vivado 12-5880] Failed to get Source File object for dynamic region BD
ERROR: [Common 17-53] User Exception: Unable to get hpfm file from project property dsa.hpfm_file or from the BD itself.
TCL Console output is attached. I tried both vcu_sdx and vcu_sdirxtx. Any help is appreciated. Thanks in advance.
09-19-2019 11:09 AM
The reason of failure is VCU SDI RX and TX design is not built in SDSoC. The Zynq UltraScale＋ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With SDSoC is actually SDx design.
So If you trying the flow you mentioned for SDI RX/TX design won't work for that.
Please move to 2019.1 TRD for new designs and features.
09-23-2019 05:46 AM
Not sure if you checked this. But let us know if you have any further questions.