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farzian
Adventurer
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Registered: ‎10-18-2014

Error injection using SEM core

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Hi everybody,

I want to inject an error to the configuration bit memory using the SEM core. Using the VIO core, I can drive inject_strobe and inject_address[39:0] of the SEM controller. After injection, controller issues the status_injection indicating the error was injected. Then, after "enter observation state" command, controller goes to the observation state. Now, I anticipate that the "error_correction_status" signal be asserted by the controller, but this signal is not asserted by the controller. I don't know what is the problem. two scenarios I am thinking:

 

1- The address that I have entered is random and design bits not affected by the injection process. If this is the reason, How I can find valid addresses to inject errors.

2-wrong injection procedure. My procedure:

      2-1 Entering idle state

      2-2 Determining the injection address

      2-3 Entering observation state and waiting for appropriate controller behavior 

I would appreciate if anyone can help me.

Thanks,

Mohammad

 

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farzian
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Registered: ‎10-18-2014

My problem was solved. It only needs to inject faults using the linear address mode and the address should be in the range of valid frame addresses. The maximum number of frames (upper bound) is reported by the controller ( MF field in the reported text generated using S command). 

 

Thanks,

Mohammad

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austin
Scholar
Scholar
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Registered: ‎02-27-2008
f, Configuration type 2 frames only are scanned. BRAM and any other memory not part of the static configuration is not scanned (but you can flip those bits). Some addresses do not exist (there are holes where no cell exists). There are also addresses which are masked (LUTRAM and SRL appear as 1's regardless).
Austin Lesea
Principal Engineer
Xilinx San Jose
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farzian
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Registered: ‎10-18-2014

Ok.

How can I determine addresses which target  type 2 frames? Is that block type field (TT) mentioned in physical frame addressing?

Thanks

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austin
Scholar
Scholar
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Registered: ‎02-27-2008
f, There is no customer support for 'bitsteam hacking.' Customers performing validation of safety critical or secure systems are supported by distributor or Xilinx field applications engineers. There is a great deal online information you may utilize, but you need to search for it.
Austin Lesea
Principal Engineer
Xilinx San Jose
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farzian
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Registered: ‎10-18-2014

I want just inject errors and verify the SEM controller behavior. Now, each address at which an error is injected, does not lead to an error correction process. I just want to know how can I inject errors to addresses that change the controller state to correction state. There is no bit stream hacking or such activities. It is just the SEM controller verification.

 

Thanks,

Mohammad 

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farzian
Adventurer
Adventurer
6,136 Views
Registered: ‎10-18-2014

My problem was solved. It only needs to inject faults using the linear address mode and the address should be in the range of valid frame addresses. The maximum number of frames (upper bound) is reported by the controller ( MF field in the reported text generated using S command). 

 

Thanks,

Mohammad

View solution in original post