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CeDeROM6502
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Registered: ‎02-05-2021

First Steps problems in Vivado 2020.2 + XC7S15-1FTGB196C + Spartan Edge Accelerator Board (SEA Board from SeedStudio)

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Hello world

I have problems running my first "from-scratch" project on XC7S15-1FTGB196C onboard SEA Board (Spartan Edge Accelerator Board from SeedStudio). In fact I also have tried Verilog codes from "Vivado Tutorial" and followed instructions presented in PDF tutorial. All steps (simulation, synthesis, implementation, bitsream) seems to go fine, I can upload bit file into the FPGA, but it does not work.

Other bit files with examples works fine so I am sure that hardware is operational.

This is the simplest Blinky code that should transfer button input into the led output. I clearly miss some step (clock? io?) that is not provided in the tutorial and it should be contained in the XDC file to work. Maybe something more needs to be clicked in GUI? I would prefer to use the minimalistic TCL/Verilog/XDC approach.

Any hints are welcome

Tomek

 

XDC file:

 

 

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports SYSCLK ];
create_clock -add -name SYSTEM_CLOCK -period 10.00 -waveform {0 5} [get_ports SYSCLK]
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports FPGA_RST]
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports FPGA_IO10 ]
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports FPGA_IO11 ]
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports FPGA_LED1 ]
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports FPGA_LED2 ]

 

Verilog source file:

 

`timescale 1ns / 1ps
module main(SYSCLK, FPGA_IO10, FPGA_IO11, FPGA_LED1, FPGA_LED2);

    input SYCLK;
    input FPGA_IO10;
    input FPGA_IO11;
    output FPGA_LED1; 
    output FPGA_LED2;
  
    wire SYSCLK;
    wire FPGA_IO10;
    wire FPGA_IO11;      
    reg FPGA_LED1, FPGA_LED2;
    
    initial begin
        $display("CeDeROM's SEA Board Example: TEST 1");
        FPGA_LED1 = 1;
        FPGA_LED2 = 1;
    end
    
    always @ (posedge SYSCLK)
    begin : main
        FPGA_LED1 <= FPGA_IO10;
        FPGA_LED2 <= FPGA_IO11;
    end

endmodule

 

Simulation Verilog file:

 

`timescale 1ns / 1ps

module main_sim();
reg SYSCLK, FPGA_IO10, FPGA_IO11;
wire FPGA_LED1, FPGA_LED2;

initial begin
$display("Simulation start. Signals: time, clk, button1, button2, led1, led2");
$monitor("%g\t %b %b %b %b %b", $time, SYSCLK, FPGA_IO10, FPGA_IO11, FPGA_LED1, FPGA_LED2);
SYSCLK = 1;
FPGA_IO10 = 0;
FPGA_IO11 = 0;
#5 FPGA_IO10 = 1; FPGA_IO11 = 0;
#5 FPGA_IO10 = 0; FPGA_IO11 = 0;
#5 FPGA_IO10 = 0; FPGA_IO11 = 1;
#5 FPGA_IO10 = 0; FPGA_IO11 = 0;
#5 FPGA_IO10 = 1; FPGA_IO11 = 1;
#5 FPGA_IO10 = 0; FPGA_IO11 = 0;
#10 FPGA_IO10 = 1; FPGA_IO11 = 0;
#10 FPGA_IO10 = 0; FPGA_IO11 = 0;
#10 FPGA_IO10 = 0; FPGA_IO11 = 1;
#10 FPGA_IO10 = 0; FPGA_IO11 = 0;
#10 FPGA_IO10 = 1; FPGA_IO11 = 1;
#10 FPGA_IO10 = 0; FPGA_IO11 = 0;
#10 $finish;
end

always begin
#1 SYSCLK = ~SYSCLK;
end

main u_main(SYSCLK, FPGA_IO10, FPGA_IO11, FPGA_LED1, FPGA_LED2);

endmodule

 

Here is the Elaborated Design:

CeDeROM6502_1-1613936277757.png

Here is the Synthesis and Implementation Design:

CeDeROM6502_0-1613936135796.png

 

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CeDeROM6502
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Registered: ‎02-05-2021

Mystery solved: I was selecting wrong part, you need to focus and select exactly the xc7s15ftgb196-1. Sorry for confusion!

 

Just a sidenote: You do not need to select Voltage Banks, VCCO, or even create a clock source for trivial projects. You only need to declare the clock input pin and that's enough

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CeDeROM6502
Visitor
Visitor
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Registered: ‎02-05-2021

Mystery solved: I was selecting wrong part, you need to focus and select exactly the xc7s15ftgb196-1. Sorry for confusion!

 

Just a sidenote: You do not need to select Voltage Banks, VCCO, or even create a clock source for trivial projects. You only need to declare the clock input pin and that's enough

View solution in original post

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