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Visitor
Visitor
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Registered: ‎05-20-2019

Floorplan wrong IO

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I'm newbie with this tool so forgive stupid questions..

 

Iv'e created a new project with schematich as high level design.

Iv'e crated a schema that involvs Flip-Flop and defined I/O. When I try to use floor plan it will not show the I/O correctly and it will only show C,D,Q pins of the FF.

If I get rid of the FF (simple delete) then FloorPlan displays all the I/O correctly.

What Am I missing ?


Full schema.JPG2.JPG

 

 

 

 

Full schema wo FF.JPG3.JPG

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Visitor
Visitor
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Registered: ‎05-20-2019

Re: Floorplan wrong IO

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UPDATE:

 

It seems like a bug with FF module.

I menually modified the UCF file (disregarded FloorPlan -IO) and it works like a charm.

 

As s newbee it is not fun at all to discover bugs since you allways think you are the one that did something wrong.. a bug was the last result I could think of but hey it is what it is lol  :-)

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Registered: ‎06-21-2017

Re: Floorplan wrong IO

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What software are you using?

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Visitor
Visitor
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Registered: ‎05-20-2019

Re: Floorplan wrong IO

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ISE Design suit 14.7 under windows 10 (I'm using the win7 installation with some modified dll files following Xilinx instructions)

 

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Visitor
Visitor
530 Views
Registered: ‎05-20-2019

Re: Floorplan wrong IO

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UPDATE:

 

It seems like a bug with FF module.

I menually modified the UCF file (disregarded FloorPlan -IO) and it works like a charm.

 

As s newbee it is not fun at all to discover bugs since you allways think you are the one that did something wrong.. a bug was the last result I could think of but hey it is what it is lol  :-)

View solution in original post

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Floorplan wrong IO

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Just as a reference, and I don' tknwo if its related to your problem or not,

Xilinx do not support the the windows 7 verison of ISE on windows 10,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor
Visitor
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Registered: ‎05-20-2019

Re: Floorplan wrong IO

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You are right and it very likly to cause the issue.

I installed the win 7 version under win 10 and renamed some dll as per Xilinx support.

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Registered: ‎01-31-2020

Re: Floorplan wrong IO

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Hello Yairyakov,

Many thanks for that input. Worked well. I had the exact problem with ISE 14.7. Strange thing was it worked well on my first 3 projects then after that, the floorplan IO no longer matches up with my ports and this only happens when I use symbols that are clocked. Spent a whole week trying to figure out what I did wrong since it worked initially with clocked devices. Very frustrating. After seeing your post, I manually edited the UCF file and deleted the wrong IO's and worked great! Thanks again! Great help.