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Explorer
Explorer
5,721 Views
Registered: ‎02-24-2016

Flop initialization & hardware reset

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Hi All,

 

Should I use an asynchronous reset in the always statement or can initiate the flop/s like following:

 

reg flop = 1'b0;

always @(posedge clock)
flop <= <some statement>;

 

In the above statement, will the flop get value '0' on the hardware reset of FPGA?

 

Thank you!

 

 

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Moderator
Moderator
10,062 Views
Registered: ‎01-16-2013

Re: Flop initialization & hardware reset

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Hi,

The initial value of register after configuration is determined by the INIT property value of FD*E cell. This value can be set in the following ways:
1. Specify initial value along with the signal declaration.
reg reg_name=1'b0;
signal signal_name : std_logic := '0';
2. Specify INIT property value after Synthesis by Tcl command:
set_property INIT 1'b0 [get_cells reg_name]
3. When there's no initial value specified with the signal declaration, the INIT value is determined by reset value. That's to say, the INIT value of FDRE and FDCE is 0, and the INIT value of FDSE and FDPE is 1.

Thanks,
Yash

P.S. Your Syntax looks good

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4 Replies
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Moderator
Moderator
5,708 Views
Registered: ‎07-01-2015

Re: Flop initialization & hardware reset

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Hi @dmitry1417,

 

By default it's 0 for all the flops. You can check the INIT value also.

Yes it will be 0. You can use below command to check also:

get_property INIT [get_cells <flop name>]

 

You can edit the value of INIT in GUI also.

Thanks,
Arpan
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Highlighted
Moderator
Moderator
10,063 Views
Registered: ‎01-16-2013

Re: Flop initialization & hardware reset

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Hi,

The initial value of register after configuration is determined by the INIT property value of FD*E cell. This value can be set in the following ways:
1. Specify initial value along with the signal declaration.
reg reg_name=1'b0;
signal signal_name : std_logic := '0';
2. Specify INIT property value after Synthesis by Tcl command:
set_property INIT 1'b0 [get_cells reg_name]
3. When there's no initial value specified with the signal declaration, the INIT value is determined by reset value. That's to say, the INIT value of FDRE and FDCE is 0, and the INIT value of FDSE and FDPE is 1.

Thanks,
Yash

P.S. Your Syntax looks good

View solution in original post

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Advisor
Advisor
5,683 Views
Registered: ‎04-26-2015

Re: Flop initialization & hardware reset

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On Xilinx FPGAs you can rely on all storage elements (flipflops, LUTRAM, block RAM) being reset to appropriate values when you reload the bitstream - which will be triggered by a hardware reset, among other things. As long as you don't require the ability to reset the system without reprogramming the FPGA, you might as well save the space and simplify timing requirements by not including a separate reset signal in the logic.

 

I'm not sure to what extent this applies to FPGAs from other companies. It wouldn't surprise me if there were a few oddball ones which actually can't handle initial values, which would mean that code using initial values is somewhat less portable. However, that's unlikely to be a big issue.

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Guide
Guide
5,675 Views
Registered: ‎01-23-2009

Re: Flop initialization & hardware reset

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you can rely on all storage elements (flipflops, LUTRAM, block RAM) being reset to appropriate values when you reload the bitstream

 

Be very careful with this... Take a look at this post on the risks of metastability and non-coherency when relying on the initialization value of a flip-flop...

 

Avrum

 

 

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