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dmitryl_home
Adventurer
Adventurer
350 Views
Registered: ‎11-08-2017

Gated Clock - why is Latch preferable over Flop for gating the clock

Hi All,

As for the Gated Clock, why is Latch preferable over Flop for gating the clock? 
 
Thank you!
 
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4 Replies
drjohnsmith
Teacher
Teacher
290 Views
Registered: ‎07-09-2009

This raises a few questions ,

in an FPGA ,

   why do you think a gated clock is good ?

   why do you think latches are good ?

   Some references would be good please

Remember ASICs are not FPGAs

 

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dmitryl_home
Adventurer
Adventurer
288 Views
Registered: ‎11-08-2017

Do you know an answer for the ASIC?

Why not to reduce a power in FPGA by using a Gated Clock? 

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drjohnsmith
Teacher
Teacher
278 Views
Registered: ‎07-09-2009

Hi @dmitryl_home

I was wondering, yes using latches in ASICs is veyr common,

     very uncomon in FPGAs 

In FPGas we have pre deinfed high speed clock routes,

    these do have the ability to be gated on / off to save power as you say, 

        BUT its not done by latches / Registers, but dedicated clock gate blocks .

As this is an FPGA forum, I will not show how out of date I am on ASICs,

 

 

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necare81
Explorer
Explorer
206 Views
Registered: ‎03-31-2016

@drjohnsmith has some very good answers for FPGAs.

For ASICs, you just need to think about the basic definition of a latch vs flop to see why a flop is not used as a clock gate.

A latch is "transparent" went enabled so it can pass the clock through, ideally without modification but in the real world there will be some delay.

A flop basically holds the value at the active clock edge until the next active clock edge. Therefore the output cannot be a "transparent" copy of the input if the input changes during the clock period. Therefore a flop gated clock would be half the frequency of the input clock.

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