04-09-2021 01:31 PM
04-10-2021 08:41 AM
This raises a few questions ,
in an FPGA ,
why do you think a gated clock is good ?
why do you think latches are good ?
Some references would be good please
Remember ASICs are not FPGAs
04-10-2021 08:50 AM
I was wondering, yes using latches in ASICs is veyr common,
very uncomon in FPGAs
In FPGas we have pre deinfed high speed clock routes,
these do have the ability to be gated on / off to save power as you say,
BUT its not done by latches / Registers, but dedicated clock gate blocks .
As this is an FPGA forum, I will not show how out of date I am on ASICs,
04-10-2021 06:11 PM
@drjohnsmith has some very good answers for FPGAs.
For ASICs, you just need to think about the basic definition of a latch vs flop to see why a flop is not used as a clock gate.
A latch is "transparent" went enabled so it can pass the clock through, ideally without modification but in the real world there will be some delay.
A flop basically holds the value at the active clock edge until the next active clock edge. Therefore the output cannot be a "transparent" copy of the input if the input changes during the clock period. Therefore a flop gated clock would be half the frequency of the input clock.