UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
7,786 Views
Registered: ‎04-23-2013

How to add existing vhdl modules in vivado HLS project?

Jump to solution

I am starting a new project on ZC702 board and Vivado.

Newbie to ZC702 and to Vivado.

Moderate experience in VHDL and ISE.

 

I want to re-use some VHDL modules that are well-tested from similar projects.

I haven't found anything that explains how to instantiate and connect VHDL modules to HLS modules, top-level or otherwise.

 

Can someone point me in the right direction?

 

Thanks,

Emmett

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
14,224 Views
Registered: ‎07-01-2015

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

Hi @emmettbradford,

 

If you are using HLS then C,C++ files can be given as an input and the generated files are .vhd or .v files which can be exported to Vivado in the form of IP, dcp etc. for later flow such as implementation.

 

If you are having VHDL files then you can use it in Vivado directly.

You can go through HLS tutorial http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug871-vivado-high-level-synthesis-tutorial.pdf

 

Let me know your requirements to help you.

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
7 Replies
Moderator
Moderator
7,785 Views
Registered: ‎06-24-2015

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

@emmettbradford,

 

You cannot give RTL files as input in Vivado HLS.

However you can package your C code in HLS into an IP and then use that IP along with your VHDL code in Vivado.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
0 Kudos
Explorer
Explorer
7,773 Views
Registered: ‎04-23-2013

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

Hi Nupurs,

Thanks for the speedy reply!

 

I see.

So the top level must be VHDL.

 

I suppose that means that the HLS module must be a separate project, and the VHDL output copied into the other VHDL project?

Do I establish the ports in HLS?

If so, how?

Or do I wait and do it in the VHDL output?

 

I have been looking for info on these issues.

Can you point me to some ug*.pdf or other resource?

 

Thanks,

Emmett

0 Kudos
Moderator
Moderator
14,225 Views
Registered: ‎07-01-2015

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

Hi @emmettbradford,

 

If you are using HLS then C,C++ files can be given as an input and the generated files are .vhd or .v files which can be exported to Vivado in the form of IP, dcp etc. for later flow such as implementation.

 

If you are having VHDL files then you can use it in Vivado directly.

You can go through HLS tutorial http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug871-vivado-high-level-synthesis-tutorial.pdf

 

Let me know your requirements to help you.

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Explorer
Explorer
7,760 Views
Registered: ‎04-23-2013

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

OK.

That should get me going.

At least I know what I am supposed to be trying to do.

 

Thanks,

Emmett

0 Kudos
Explorer
Explorer
7,518 Views
Registered: ‎04-23-2013

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

The interface of my VHDL modules is AXI but also discrete signals and vectors.

Isn't there a way to "package" my vhdl modules as "IP" that can then be used in Vivado HLS?

 

 

Please list the best search terms.

 

Thanks,

Emmett

Tags (1)
0 Kudos
Moderator
Moderator
7,513 Views
Registered: ‎07-01-2015

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

Hi @emmettbradford,

 

HLS Input is C,C++ files whereas o/p is IP,dcp which can be used as an i/p to Vivado.

I didn't get your query correctly. You can use VHDL file in Vivado along with the Vivado HLS IP.

 

Please post your query in HLS board to target correct audience.

 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
7,511 Views
Registered: ‎04-23-2013

Re: How to add existing vhdl modules in vivado HLS project?

Jump to solution

Thanks,

Emmett

0 Kudos