12-27-2013 08:22 PM
I'm attempting to use the AXI-Stream Fifo in Vivado 2013.4. I've hooked it up in the usual way through an AXI Interconnect to a M_AXI_GP0 on the Zynq:
But when I run Validate Design, I get the following critical errors.
My first thought was to recustomize the processor and change the Thread ID Width from 12 to 4:
I have no idea if this is a good idea, but in any event it won't let me change it. Any suggestions on how to use the AXI-Streaming FIFO would be appreciated.
12-28-2013 09:26 AM - edited 12-28-2013 09:32 AM
Your problem is between the processor and the AXI interconnect as the fifo is not connected to the processor directly. Your best bet is to change the id width of the interconnect slave axi bus. How did you get the interconnect? I just added a zynq and a streaming fifo to a block design, and after block & connection automation validate design worked OK for me.
12-28-2013 03:55 PM
I suspect you're correct, but I did not see anything in the AXI Interconnect to allow setting the TID width.
I should note that if I leave the "AXI-Stream Fifo" at "AXI4 Lite", it works:
Only the AXI has the TID width:
Which interface did you use? I need the full AXI4 with bursting in order to get the higher performance listed on page 12 of the Fifo datasheet (370 MByte/sec vs 78 MByte/sec).
04-17-2015 07:04 AM
Did this ever get resolved? I am trying to do the same thing in Vivado 2014.4. I have the system hooked up almost identically to the diagram. I used the connection automation for everything, and both axi-lite address and axi-full address appears in my address editor. Whenever I try to write to the TDFD register (transmit data fifo register) via memory mapping to the AXI-Full interface, the software crashes. No problem accessing the registers via AXI-lite.
Any suggestions? I also need to utilize the AXI-full interface to achieve bandwidth.