cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
paul.tutzu
Visitor
Visitor
1,665 Views
Registered: ‎05-09-2017

How to create a "debugable" IP Core

Hi,

 

I have a design with Block Design. I want to "Package my current project" and to use it in the next project as an IP. I packaged it and then inserted it in the new project.

 

Now I want to debug the main/upper Project. The problem i can see only the Netlist of the IP. Is there a way to access from the main/upper Project the Block Diagram of my IP in order to use Logic Analyzer on some of the internal buses.

 

How is one suppose to debug a Design which contains a hierarchy with several levels of custom IPs? For example

 Main Project

IP1                  IP2

IP1.1   IP1.2      IP2.1  IP2.2

 

Is there a way to access from the Main Project to lower IPs Block Design and RTL code. And not the Netlist.

 

Thanks

0 Kudos
0 Replies