I have a design with Block Design. I want to "Package my current project" and to use it in the next project as an IP. I packaged it and then inserted it in the new project.
Now I want to debug the main/upper Project. The problem i can see only the Netlist of the IP. Is there a way to access from the main/upper Project the Block Diagram of my IP in order to use Logic Analyzer on some of the internal buses.
How is one suppose to debug a Design which contains a hierarchy with several levels of custom IPs? For example
IP1.1 IP1.2 IP2.1 IP2.2
Is there a way to access from the Main Project to lower IPs Block Design and RTL code. And not the Netlist.