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Visitor rcmemo
Registered: ‎04-02-2009

How to implement an IP core generator with System Generator

I'm working with System Generator and with a ADM-XRC card from Alpha-Data which contains a Virtex IV FPGA.


I have succesfully implemented some hdl designs through hardware cosimulation but when I used an IP core in the design, this didn't work.


The IP core I used is the DAFIR V9.0, and I used it as a black box. I added the neccesary files in the configuration file of the black box, and the software cosimulation of this is correct,


but the hardware cosimulation is not. I think the problem can be the configuration of the CLK, CE, pins.


I hope somebody can give me some advice.



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