UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor nmpr
Visitor
10,958 Views
Registered: ‎02-04-2009

How to load verilog include file

Jump to solution

Hi,

 

I am trying to load a big verilog design into FPGA using ise 9.1 .

Some verilog file used  an `include declaration for files.

When I synthesis the code, the tool can not find these files.

I have try to load these file directly into use but the tool refuse.

There should be a way a declare a search path so the tool can find and use them.

What is the best way to solve this issue.

 

Thanks,

 

nitzan

0 Kudos
1 Solution

Accepted Solutions
Participant jared.chen
Participant
12,753 Views
Registered: ‎05-12-2008

Re: How to load verilog include file

Jump to solution

Hello,

There is  an option named "Verilog Include Directories" in Synthesis Properties.

Verilog Include Directories (Advanced)

Specifies the discrete paths to your Verilog include Directories. To specify multiple paths, type in multiple paths, using the pipe (|) symbol to separate each path. You can also click the Browse button to browse to the first path and type in subsequent paths, using the pipe (|) symbol to separate each path. There is no default.

 

Regards,

Jared

 

 

3 Replies
Participant jared.chen
Participant
12,754 Views
Registered: ‎05-12-2008

Re: How to load verilog include file

Jump to solution

Hello,

There is  an option named "Verilog Include Directories" in Synthesis Properties.

Verilog Include Directories (Advanced)

Specifies the discrete paths to your Verilog include Directories. To specify multiple paths, type in multiple paths, using the pipe (|) symbol to separate each path. You can also click the Browse button to browse to the first path and type in subsequent paths, using the pipe (|) symbol to separate each path. There is no default.

 

Regards,

Jared

 

 

Visitor nmpr
Visitor
10,920 Views
Registered: ‎02-04-2009

Re: How to load verilog include file

Jump to solution

Thanks for the reply.

This does solve the problem using the ise!! 

How can I declare it in a TCL script?

 

Thanks,

 

Nitzan

0 Kudos
Participant jared.chen
Participant
9,958 Views
Registered: ‎05-12-2008

Re: How to load verilog include file

Jump to solution
project set "Verilog Include Directories" directory_path
0 Kudos