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joelschad
Adventurer
Adventurer
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Registered: ‎05-18-2018

How to set port types on custom IP

 

I want to route some of the ports of a homebrew SPI IP block to a Utility Buffer IP block. However, this is throwing (non-critical) warnings like:

WARNING: [BD 41-1731] Type mismatch between connected pins: /COMS_SPI_master/mosi(undef) and /COMS_SPI_MOSI_ds_buf/OBUF_IN(clk)

1) Under what conditions does this actually matter?

2) How can I set the port types in my HDL? In the Package IP screen, I only see std_logic and std_logic_vector in the 'Type Name' column of the Ports and Interfaces screen.

Thanks.

 

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surajc
Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

@joelschad 

How can I set the port types in my HDL?

see the following snapshot

Capture.JPG

Under what conditions does this actually matter?

These details which you provide through design entry are used by the tool to make proper use of the target device

for example, if mosi and OBUF_IN[0:0] both are of the type clock, then tool will use dedicated clock routing resources during implementation phase,

else if not mentioned the type clock then tool will use local routing resources.

What we give input to the tool during design entry is used for best utilization and performance of the design on the device.

 

--Suraj

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joelschad
Adventurer
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Registered: ‎05-18-2018

Thanks.

If I have a data (not clock) signal coming into a Utility Buffer block from a homebrew IP block, should I set the output type of my IP block to clock to 'clk' even though it's not a clock?

Alternatively, is there a way to change the expected input signal type in the Utility Buffer instead of changing the output type of my IP?

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