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Participant saurabhsk
Participant
7,309 Views
Registered: ‎02-17-2009

How to skip initialization sequence for DDR/DDR2 models for gate level simulation

Hi ,

 

  I am using DDR/DDR2 XIlinx IP models for specific technology. I have to do gate level simulation. It looks , it requires around 500 ms initial cycle to start the sequence in gate level simulation. 

 

  Is there any parameter support to avoid this long time period as at RTL simulation it is not taking such long time.

 

Thanks in advance for your help.

 

-Saurabh

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6 Replies
Advisor eilert
Advisor
7,305 Views
Registered: ‎08-14-2007

Re: How to skip initialization sequence for DDR/DDR2 models for gate level simulation

Hi Saurabh, Don't worry about the time, It's the number of events that count. The simulation of the first 500ms will be quite fast since there's not much happening, but when the DRAMs start working as intended the simulation will drastically slow down. You are dealing with models that show physical behavior. Maybe you have DDR-RAM models connected to the RAM-Controller IP. Both models have to match. Have a nice simulation Eilert
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Participant saurabhsk
Participant
7,306 Views
Registered: ‎02-17-2009

Re: How to skip initialization sequence for DDR/DDR2 models for gate level simulation

Hi Eilert,

 

  Thanks for quick prompt.

 

Actually it is taking "200us + 500 ms + 100 ms in simulation" IP. And the RTL simulation time difference and gate level simulation time difference is huge.

 

So is it possible to get a any parameter control from the top to speed up the execution. Like for AURORA IPs there there is parameter exist to speed up the gate level simulation.

 

-Saurabh

 

 

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Xilinx Employee
Xilinx Employee
7,294 Views
Registered: ‎10-23-2007

Re: How to skip initialization sequence for DDR/DDR2 models for gate level simulation

What FPGA family are you using?  Did you create your memory interface IP through MIG?  If so, which version?

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Participant saurabhsk
Participant
7,293 Views
Registered: ‎02-17-2009

Re: How to skip initialization sequence for DDR/DDR2 models for gate level simulation

 

Hi,

 

  I generated it from ISE 11.4 for xcv5 . I jusr generate DDR2 MIG Model and trying to see the gate level simulation for some requirement and looking for some parameter control from top to speed up my gate level simulation , just to avoid initial 500 ms simulation cycles.

 

-Saurabh

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Historian
Historian
7,286 Views
Registered: ‎02-25-2008

Re: How to skip initialization sequence for DDR/DDR2 models for gate level simulation

 


@saurabhsk wrote:

Hi ,

 

  I am using DDR/DDR2 XIlinx IP models for specific technology. I have to do gate level simulation. It looks , it requires around 500 ms initial cycle to start the sequence in gate level simulation. 

 

  Is there any parameter support to avoid this long time period as at RTL simulation it is not taking such long time.

 

Thanks in advance for your help.

 

-Saurabh


You might be able to hack the model for the memory so that it does not need the initialization steps. Just make sure that it does have all of the internal registers set to appropriate and correct values.

 

----------------------------Yes, I do this for a living.
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Advisor eilert
Advisor
7,165 Views
Registered: ‎08-14-2007

Re: How to skip initialization sequence for DDR/DDR2 models for gate level simulation

Hi Saurabh, RTL Sim and Gate level always have a big time difference. I hope my last posting did not give the impression that I mean it wouldn't be so. But still the simulation time depends on the number of signal events, that trigger calculations. During some initialisaton phase, this number should be low compared to normal activity, so the simulation speed for this phase will be high, compared to the simulation speed that you observe during normal operation of the design. simulation speed = simulated time / simulation time But it may be that the simulator wastes time computing results of idling clocked processes of the rest of your system. One dirty trick may be to stop the clock for idling portions of your system during the 500 ms initialisation phase. No events = No processes triggered (gates are processes too, just in libraries) = Increased simulation speed Have a nice simulation Eilert
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