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dxdanielson
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Registered: ‎09-16-2010

How to trigger a process on the rising edge of any of multiple inputs.

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I’m writing VHDL for a Xilinx CPLD and I need to trigger a process on the rising edge of any of four different inputs.

 

The following doesn’t work, but it shows what I want to do.

If (rising_edge(in1) or rising_edge(in2) or rising_edge(in3) or rising_edge(in4)) then…

 

Any of the inputs may be high or low when there's a rising edge on another. 

 

Any ideas?

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sonicwave
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Registered: ‎11-26-2008

I have only very little experience with CPLDs, so I'm not sure this will work. But if you have a fast enough clock available, you could simply continuously sample the four signals, compare each of them to their previous value, and trigger the appropriate statements if a change is detected.

 

Without a clock, if you can get a delayed version of the four inputs, you might be able to XOR the current and delayed versions, do an OR on the results, and use that as a clock?

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eilert
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Registered: ‎08-14-2007

Hi,

you are trying to do somthing weird, but with the limited ressources of a CPLD one has to be "creative" sometimes. :-)

 

The problem is that the synthesis tool just don't understands your synchronous description.

(There can only be one clock in a synchronous description for a process)

 

My first intention was to recommend something like this:

 

ff_clk <= in1 or in2 or in3 or in4;  -- concurrent assignment outside the process

...

if rising_edge(ff_clk) then...

 

Synthesis will accept it, but this will only work when you have short pulses which do not overlap. Can you guarantee that?

 

If your signals have a more randomly character you may have to rethink your approach.

Maybe it's helpful to draw a sketch of how you would solve the problem with ordinary gates and FFs.

You will quickly see that it's not trivial to find a generic solution.

 

Have a nice synthesis

  Eilert

 

 

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sonicwave
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9,053 Views
Registered: ‎11-26-2008

I have only very little experience with CPLDs, so I'm not sure this will work. But if you have a fast enough clock available, you could simply continuously sample the four signals, compare each of them to their previous value, and trigger the appropriate statements if a change is detected.

 

Without a clock, if you can get a delayed version of the four inputs, you might be able to XOR the current and delayed versions, do an OR on the results, and use that as a clock?

View solution in original post

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dxdanielson
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Registered: ‎09-16-2010

Interesting. I didn't realize you could use 'event on a combined signal. But it makes sense. Unfortunately I'm looking at a quadrature signal so there is overlap in the pulses.

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dxdanielson
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Registered: ‎09-16-2010

Here' s a code snippet of a working solution.

 

if (rising_edge(clk)) then

      s1curr <= s1;

      s2curr <= s2;

      s3curr <= s3;

      s4curr <= s4;

      s1prev <= s1curr;

      s2prev <= s2curr;

      s3prev <= s3curr;

      s4prev <= s4curr;

      if ((s1curr = '1' and s1prev = '0') or

          (s2curr = '1' and s2prev = '0') or

          (s3curr = '1' and s3prev = '0') or

          (s4curr = '1' and s4prev = '0')) then    -- a rising egde one of of the four step inputs was detected.

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