How to use built-in RAM blocks?

[brilas]

Hi,

Could someone please enlighten me how to use built-in RAM blocks rather than implementing it?

Do I have to use "Core Generator & Architecture wizard" or what?

Ignas

[eteam00]

Using the Core generator is quick simple.

If you want to roll your own, then (from within ISE) EDIT > Language Templates

check the section for <Verilog | VHDL> / Device Primitive Instantiation / <FPGA family> / RAM/ROM

Also check the user docs for the FPGA family you are using.  There might be a memory user guide or something like that.

-- Bob Elkind

[brilas]

Mhm, thats a nice hint, Bob.

A few more questions:

1) But how about interconnection between built-in RAMS and my FPGA design? Do I have to create new module in my desing, copy that code from language template, make some changes in my needed port declarations (marked red) and that will be enough for synthesizer to recognize that I want to use built-in RAMS and NOT implement it in FPGA?

Or do I have to make more changes in some other files, for example some kind of wiring or something?

 2) And how about viewing RTL schematic. Will I be able to see all connections of my fpga design with built-in RAMs or not ?

port map (
      CASCADEOUTA => CASCADEOUTA, -- 1-bit cascade output
      CASCADEOUTB => CASCADEOUTB, -- 1-bit cascade output
      DOA => DOA,      -- 32-bit A port Data Output
      DOB => DOB,      -- 32-bit B port Data Output
      DOPA => DOPA,    -- 4-bit  A port Parity Output
      DOPB => DOPB,    -- 4-bit  B port Parity Output
      ADDRA => ADDRA,  -- 15-bit A port Address Input
      ADDRB => ADDRB,  -- 15-bit B port Address Input
      CASCADEINA => CASCADEINA, -- 1-bit cascade A input
      CASCADEINB => CASCADEINB, -- 1-bit cascade B input

      .... );

Regards,
Ignas

[rcingham]

Don't change the names on the left-hand side of the port map.

Have you done much VHDL?

[brilas]

I'm some kind of self-educated begginer and I'm more familiar with Verilog language rather than VHDL...

[eteam00 · Accepted solution]

I'm some kind of self-educated begginer and I'm more familiar with Verilog language rather than VHDL...

Dear beginner:

some advice:

• Stick with Verilog (easier to learn than VHDL if you are just starting)
• No schematics.  None.

But how about interconnection between built-in RAMS and my FPGA design?

Primitives are "connected" to your design as per the template.  That's what "template" means.

Do I have to create new module in my design

No.

copy that code from language template

Yes.

make some changes in my needed port declarations (marked red)

You are not allowed to change port names of instantiated primitives.

and that will be enough for synthesizer to recognize that I want to use built-in RAMS and NOT implement it in FPGA?

You need to understand what the term "primitive" means.  A primitive is an explicit instantiation, and is not interpreted by the synthesiser.

Or do I have to make more changes in some other files, for example some kind of wiring or something

Here's a suggestion:  Experiment with primitives which are simple (e.g. flip-flops, output buffers).  Learn by experimentation (trial and error).  It won't take long to get the hang of it.  Also spend some time with "reference" design source code (e.g. XAPP495).  You can learn much from others' code, at this stage.

And how about viewing RTL schematic. Will I be able to see all connections of my fpga design with built-in RAMs or not ?

Don't bother with schematics.  This will give you more sources of confusion and distraction.  Stick with Verilog until you are comfortable with it.

-- Bob Elkind

[brilas]

Thank you for your answers, Bob. Now I know where to start  :)

Have a nice day,

Ignas

[brilas]

There are few good examples about how to create CORE generator module in "in depth tutorials" of your chosen software:

http://www.xilinx.com/support/techsup/tutorials/index.htm

Hope this will help for somebody ;)