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Visitor
Visitor
325 Views
Registered: ‎11-05-2020

I/O Planning before Synthesis

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Hi there,

 

is there a possibilty to set the FPGA Pin before Systhesis for an external port in block design? After that i want to export the block design. If the first step is possible, is there a way to export the contraints together with the block design?

 

Kind regards,

Samuel

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-13-2020

Hi @samlei 

You can set the FPGA pins before synthesis when you create a new project: select "Io Pin Planning Project". I believe you have to export the constraints separately from the block design file. 


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pin_assignment.JPG
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Xilinx Employee
Xilinx Employee
262 Views
Registered: ‎02-13-2020

Hi @samlei 

You can set the FPGA pins before synthesis when you create a new project: select "Io Pin Planning Project". I believe you have to export the constraints separately from the block design file. 


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pin_assignment.JPG
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Teacher
Teacher
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Registered: ‎07-09-2009
@samlei

A big point. or two.
I'm assuming your using a FPGA , not a CPLD.
Were assuming Vivado, tell us if tis ISE.

Almost all pins on FPGAs are multi purpose, BUT some can do things better than other pins. I.e. Clocks really do like the clock pins, although all pins can be used as clocks, and clock pins can be used as IO.

There are also routing rules and bank rules,

The bigger FPGAs are strangely more attune to pins being randomly set, the smaller ones like artex have a few features that make a some pin mapping take up more resources than others.

the Io planer is a great little tool, if you know the chip or have done it a few times,
it for one stops you crossing a bank with different Io voltages, and stops you miss assigning differential pairs,

But , and apologies here, I'm guessing ,as you are asking, then you are relatively new to this. I'm also guessing that you are not using a pre existing board as they tend to come with pre assigned top level pin files.

If that is the case, I'd strongly suggest that you make the top level block of your design first, and try out fitting. See what banks work and dont.

certainly do not go to layout till you have a fairly complete top level.
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Visitor
Visitor
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Registered: ‎11-05-2020

Thanks a lot, that was obvious...

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