@samleiA big point. or two.
I'm assuming your using a FPGA , not a CPLD.
Were assuming Vivado, tell us if tis ISE.
Almost all pins on FPGAs are multi purpose, BUT some can do things better than other pins. I.e. Clocks really do like the clock pins, although all pins can be used as clocks, and clock pins can be used as IO.
There are also routing rules and bank rules,
The bigger FPGAs are strangely more attune to pins being randomly set, the smaller ones like artex have a few features that make a some pin mapping take up more resources than others.
the Io planer is a great little tool, if you know the chip or have done it a few times,
it for one stops you crossing a bank with different Io voltages, and stops you miss assigning differential pairs,
But , and apologies here, I'm guessing ,as you are asking, then you are relatively new to this. I'm also guessing that you are not using a pre existing board as they tend to come with pre assigned top level pin files.
If that is the case, I'd strongly suggest that you make the top level block of your design first, and try out fitting. See what banks work and dont.
certainly do not go to layout till you have a fairly complete top level.
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