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Newbie danielct
Registered: ‎03-19-2018

IP_Flow 19-4965 - Critical Warning board mismatch

Hi, I am having some problems with IPs that I downloaded from Digilent's GitHub. I downloaded the 'vivado-library-master' to use some of their Pmod IPs. Upon use the design gets verified fine, however when it comes to Synthesis or Implementation I get this critical warning:


"CRITICAL WARNING: [IP_Flow 19-4965] IP PmodHYGRO_axi_iic_0_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'em.avnet.com:zed:part0:1.3'. Please update the project settings to match the packaged IP. "


I have tried finding a board of value 1.1 online but they all seem to be 1.3 now and alternatively I have looked at doublechecking the IPs that I am using are correct. On GitHub they say that they are compatible with Vivado 2017.4 and 1.3 seems to be the only board version available on 2017.4, so I'm not entirely sure where this issue is coming from. The follow up message from the tcl console is:

"INFO: [IP_Flow 19-3420] Updated PmodHYGRO_axi_iic_0_0 to use current project options "


Which made me think it dealt with the issue however, if I continue through with the Synthesis  and Implementation the project is unable to produce a bitstream for me. 


I have tried attaching a compressed version of the project to this post but it is too large, however here is a link to the library on Github I'm using:



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2 Replies
Registered: ‎11-09-2015

Re: IP_Flow 19-4965 - Critical Warning board mismatch

Hi @danielct,


The board files fior the Arty and the steps to install them are here. The latest version for this board is 1.1 so I am not sure what you were looking at...



Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎06-14-2010

Re: IP_Flow 19-4965 - Critical Warning board mismatch

Hello @danielct,


This topic is still open and is waiting for you.


If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 


If this is not solved/answered, please reply in the thread.


Thanks in advance and have a great day.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
Don’t forget to reply, kudo, and accept as solution.
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