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Registered: ‎10-03-2019

IP Interator referencing issue

ERROR: [filemgmt 56-190] Failed to uniquely resolve reference. Multiple different modules were found that match the name 'sync_pkt_rw_fifo_MxN'

Getting the above error in a block design where I have replicated a small block multiple times in a larger block design.

There is only one module named sync_pkt_rw_fifo_MxN, it is a verilog rtl module. It is instantiated multiple times in the original block design. There were no issues with build, synthesis, simulation of the original bd.


Vivado v2019.1 (64-bit) SW Build: 2552052 on Fri May 24 14:49:42 MDT 2019 IP Build: 2548770 on Fri May 24 18:01:18 MDT 2019

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Registered: ‎10-03-2019

This issue is now resolved.

It appears that Vivado does not like having a verilog module instantiated within another verilog module AND instantiated as a separate instance in a bd. I resolved the issue by creating a separate veriliog module: module_name_bd.v. I used module_name.v when instantiating it withing another module and module_name_bd.v when instantiating it directly in the bd. A bit of a nuicance from a source management perspective but the errors went away...

If anyone disagrees that this is an issue with block designs in IP integrator please let me know.



Registered: ‎08-13-2020

A workaround that does not duplicate code is to, for each module 'mod' where 'mod' is used both in other module definitions and in block diagrams, define a wrapper module 'mod_wrapper' for the module.  Then use 'mod' for instances in module definitions, and 'mod_wrapper' for instances in block-diagrams.  Add the wrapper definition to the same file.  Existing hdl is not broken.

Tested in Verilog and Vivado 2019.1.

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