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chevalier
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Registered: ‎10-07-2011

IP Packager hanging on types and functions from ieee.math_real

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Hi folks,

 

I'm using Vivado 2016.4 on Win10-64. I have a code block that I'd like to package. The top-level has generics that are assigned numerical values (I mean plain numbers, not equations), and ports that are sized accordingly.

 

The index range of the ports are using types and functions from the ieee.math_real package to compute boundaries. This is to allow alignment of subfields to byte boundaries. This is shown below.

 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;

entity MyBlock is generic ( A: integer; B: integer; C: integer ); port ( AXIS_ACLK: IN std_logic; S_AXIS_TDATA: IN std_logic_vector(integer(ceil(real(2 * C + B * A) / real(8))) * 8 - 1 downto 0); ... M_AXIS_TDATA: OUT std_logic_vector(integer(ceil(real(B * A) / real(8))) * 8 - 1 downto 0); ... );

 

For example, with A=10, B=3 and C=16, we should get S_AXIS_TDATA(63 downto 0) and M_AXIS_TDATA(31 downto 0). That works fine in the standard RTL flow, but doesn't package. Packaging is reporting the error below.

 

  • [IP_Flow 19-627] Port 'S_AXIS_TDATA': XPath expression failed: Unsupported function call or array usage "real" found in expression "((integer(ceil((real(((2 * spirit:decode(id('MODELPARAM_VALUE.C'))) + (spirit:decode(id('MODELPARAM_VALUE.B')) * spirit:decode(id('MODELPARAM_VALUE.A'))))) / real(8)))) * 8) - 1)".

It seems the packager doesn't like the ieee.math_real stuff.

 

How can I workaround that?

 

Thanks!

 

Claude

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prathikm
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Registered: ‎09-15-2016

Hi @chevalier,

 

Just to suggest some info, I believe from UG1118 page. 11 it is mentioned that the IP packager requires that the IP ports are self-contained; therefore, the IP packager does not support custom functions defined in your HDL.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Also, a CR-973646 (active) was filed for requesting more information in UG1118 on how to use supported XPATH functions to work for both packaging and non-packaging flow. The way I see is to use fix data bits like this:

 

snap.PNG

 

But let us wait for any further suggestions/comments from our forum's expert team.

 

Regards,
Prathik


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prathikm
Moderator
Moderator
9,616 Views
Registered: ‎09-15-2016

Hi @chevalier,

 

Just to suggest some info, I believe from UG1118 page. 11 it is mentioned that the IP packager requires that the IP ports are self-contained; therefore, the IP packager does not support custom functions defined in your HDL.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Also, a CR-973646 (active) was filed for requesting more information in UG1118 on how to use supported XPATH functions to work for both packaging and non-packaging flow. The way I see is to use fix data bits like this:

 

snap.PNG

 

But let us wait for any further suggestions/comments from our forum's expert team.

 

Regards,
Prathik


--- Please mark the Answer as "Accept as solution" if information provided is helpful ---
--- Give Kudos to a post which you think is helpful and reply oriented. ---

 

 

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chevalier
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Registered: ‎10-07-2011

Dear @prathikm,

 

Thanks for your reply. So, if I understand well, UG1118 is basically saying to get rid of the Verilog

 

output [ceil_log2(max_count)-1:0] count;

 

and use the XPATH below

 

ceiling(log(2, $max_count))-1

 

But the XPATH expression can't be part of the HDL file, and the original HDL code can't remain as is. So, how would the Verilog file be changed?

 

output [???:0] count;

 

And where is the XPATH expression going to be entered?

 

Are these explanations the intent of the CR?

 

I do have a side question. VHDL-2008 allows for unconstrained arrays. I guess the UG1118 "self-contained" wording is prohibiting unconstrained arrays. Right? So if the top-level unconstrained array is getting constrained by the lower-level code, is it still prohibited?

 

We are in 2017. VHDL-2008 will celebrate its 9th birthday this year. It's bad that it is not better supported. It's really an improvement! The CR should request better support for VHDL-2008 in the IP Packager... That's what users (customers) really need. For synthesis and simulation, we can use third-party tools... but for IP Packager, we are stuck with Xilinx.

 

Thanks again,

 

Claude

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syedz
Moderator
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Registered: ‎01-16-2013

@chevalier,

 

Factory is actively working to fully support VHDL-2008 in future release of Vivado.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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chevalier
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Registered: ‎10-07-2011

Hello @syedz,

 

Thanks for letting us (the whole community) know. This is REALLY GOOD news to know about Xilinx commitment. It would be nice to know what the exact roadmap is.

 

Have a good day!

 

Claude

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prathikm
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Registered: ‎09-15-2016

Hi @chevalier,

 

Also regarding the initial query: Yes, the explanations you asked for is the intent of the CR. We do not have examples & clear documented information on usage of XPATH functions and hence the CR-973646 is filed. This will give us a clear idea from the factory on usage of supported XPATH functions to work for both packaging and non-packaging flow.

 

Regards,

Prathik

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chevalier
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Registered: ‎10-07-2011

Hello Prathik (and the whole community!),

 

As explained above, I have some code that is defining an IP that I'm trying to package. When using the Vivado IDE to go through the IP Package process, errors are reported because of some "ieee.math_real" functions that need to be replaced by XPATH functions. I can do that easily and complete the IP Packaging process successfully.

 

However, I would like to do the whole thing from a tcl script, without having to edit fields in the GUI or, even better, without having to launch the GUI at all.

 

The script we created goes fine until the "ipx::package_project" command is run. The command is failing because of the math_real stuff, and execution is aborted with the message below:

 

source make.tcl
# ipx::package_project -quiet -root_dir ../sources -vendor xxx -library yyy -taxonomy /yyy -force 
# set_property vendor_display_name yyy [ipx::current_core]
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    while executing
"rdi::set_property vendor_display_name yyy {component component_1}"
    invoked from within
"set_property vendor_display_name yyy [ipx::current_core]"
    (file "make.tcl" line 5)

The above suggests to refer to "earlier errors", but there are none reported.

 

 

The problem is that I can't apply any tcl command to resolve the math_real to XPATH conversion before the above command is executed. We thought the -quiet option would help but it doesn't.

 

Another working flow is as follow:

1. Run a first tcl to build the Vivado project from the source files.

2. Click the <Tools -> IP Package> command. The IP Package project is launched and errors are reported.

3. Run a second tcl script to apply all the corrections.

4. Click OK to complete packaging of the IP.

 

Is there a way to do the whole thing from a single script, without having to interact with the GUI?

 

Thanks!

 

Claude

 

 

 

 

 

 

The script goes fine until the

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chevalier
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Registered: ‎10-07-2011

Hello all,

 

I finally modified my HDL to avoid using the ieee.math_real library. This line of code (where gK, gM and GN are INTEGER generics):

 

  S_AXIS_TDATA: in STD_LOGIC_VECTOR(8*(ceil(REAL(2*gK)/8.0) + ceil(REAL(gM*gN)/8.0)) - 1 downto 0);

 

has been changed to

 

  S_AXIS_TDATA: in STD_LOGIC_VECTOR(8*(ByteLength(2*gK) + ByteLength(gM*gN)) - 1 downto 0);

 

where ByteLength is the function below that is NOT using the math_real stuff, but relies on the usual "rem" operator:

  function ByteLength(N: natural) return natural is
    variable Y: natural := N / 8;

  begin
    if ((N rem 8) /= 0) then
      Y := Y + 1;
    end if;

    return Y;
  end function ByteLength;

 

Again, everything simulates, synthesizes and implements just fine. Hardware testing is successful as well. But IP Packaging still fails, complaining about ByteLength not being an XPATH function:

• [IP_Flow 19-627] Port 'S_AXIS_TDATA': XPath expression failed: Unsupported function call
or array usage "ByteLength" found in expression "((8 * ByteLength((spirit:decode(id(
'MODELPARAM_VALUE.gCHANNELS')) * spirit:decode(id('MODELPARAM_VALUE.gCHANNEL_WIDTH')))))
- 1)".

 

So, it seems like the problem is NOT strictly related to the use of the ieee.math_real NOR that of VHDL-2008, but simply related to the fact that the IP Packager doesn't allow ANY HDL function (ie non XPATH) to be used to size an array.

 

So, this brings me back to my previous post just above this one. When the IP Package process is started, I know the tcl commands that are needed to resolve all the issues. I can create a script containing all of those. But is there a way to run all these BEFORE the IP Packaging process is launched?

 

Cheers,

 

Claude

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