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andrewjcart
Explorer
Explorer
15,684 Views
Registered: ‎09-16-2010

IP keeps resynthesizing in Vivado in OOC mode

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I have found that even in the default out-of-context mode, the IP occasionally wants to regenerate. This causes a problem since I have modified the IP in some cases by changing a few parameters and when Vivado regenerates, it overwrites my changes. Also, it is pretty annoying to have all these files continually changing in the versioning repository. I haven't narrowed down when extactly it wants to regenerate the cores, but I think it might have something to do with the cores being shared between different Vivado projects. Is there a known issue with this? Ideally, I would like to generate them once and never again, unless explicitly done. I believe this is the intended flow, so maybe there are still some bugs to work out for Vivado. 

 

"The OOC flow is the default flow because of two main benefits:
• It improves synthesis run times because you synthesize the IP only once."

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug896-vivado-ip.pdf

 

 

Andrew
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swolf
Xilinx Employee
Xilinx Employee
25,420 Views
Registered: ‎07-09-2013

Also... if you want to prevent regenerating an IP you can do two things:

- use TCL to "lock" the IP:  set_property IS_LOCKED [ get_files myip.xci ]

OR

- in the file system make the xci and corresponding xml files read only: chmod 444 myip.xci myip.xml

 

 

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viviany
Xilinx Employee
Xilinx Employee
15,680 Views
Registered: ‎05-14-2008

some suggestions from me:

1. For the IPs that you've modified some parameters in it, uncheck the IS_MANAGED property of the xci file to prevent re-generating.

2. Make the IP local to the project directory so that it is not shared between different projects.

 

I'm not sure the reason the IPs are occasionally re-generated. This is actually a Design Entry issue. I'll move your post to Design Entry board. Hope someone on that board can help you more.

 

-Vivian

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andrewjcart
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Registered: ‎09-16-2010

I unchecked "is managed" and it actually caused the core to be resynthesized again. Maybe this is the last time? Who knows. This is a pretty big hit on compile time, especially for cores like MIG.

 

 Thanks for the tips Vivian. 

Andrew
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vemulad
Xilinx Employee
Xilinx Employee
15,611 Views
Registered: ‎09-20-2012

Hi @andrewjcart 

 

If your issue is resolved, please close the thread by marking the answer.

 

Thanks,

Deepika.

Thanks,
Deepika.
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andrewjcart
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Registered: ‎09-16-2010

The recompiling of ip cores was due to an option that Vivado pops up the very first time you run synthesis, asking you if you want to regenerate out of date OOC modules before synthesis. It remembers this setting and never pops up again. I must have said "yes" the first time, not knowing what it was talking about. I only noticed this because I deleted the entire Vivado cache in my Windows AppData/Roaming folder due to a separate issue with Vivado constantly crashing and unable to synthesize. 

Andrew
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andrewjcart
Explorer
Explorer
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Registered: ‎09-16-2010

Does anyone know how to change the auto-rebuild IP setting without deleting the APPDATA folder? I assume it's hidden, along with everything else, in some obscure tcl command. The Xilinx IP in my project keeps randomly wanting to rebuild and it's driving me absolute bonkers. This is a major hit to development time. In fact, sometimes the OOC IP hang when implementing or crash Vivado. I'm contemplating disabling OOC altogether, but am worried I will face other bugs. 

Andrew
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vemulad
Xilinx Employee
Xilinx Employee
15,417 Views
Registered: ‎09-20-2012

Hi Andrew,

 

In Vivado go to Tools --> options. You can change the default settings here. See below.

 

Untitled.png

 

Thanks,

Deepika.

Thanks,
Deepika.
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swolf
Xilinx Employee
Xilinx Employee
25,421 Views
Registered: ‎07-09-2013

Also... if you want to prevent regenerating an IP you can do two things:

- use TCL to "lock" the IP:  set_property IS_LOCKED [ get_files myip.xci ]

OR

- in the file system make the xci and corresponding xml files read only: chmod 444 myip.xci myip.xml

 

 

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andrewjcart
Explorer
Explorer
15,189 Views
Registered: ‎09-16-2010

It seems to want to regenerate IP after adding new unrelated files to the project, though it may be a random bug when resetting synthesis run. I have disabled the managed property. Though it didn't reset all IP cores, just 2 of 6. 

 

For example, I did a full build. After it had completed, I edited a couple files, and added two non-IP vhdl source files to the project. I then reset synthesis run and started the build. The IP for mig7 and block memory generator had somehow reset themselves and started spinning through synthesis again.  Adds about 20 min to current build. 

 

 The only thing I haven't tried is a chmod on the ip. Simple enough, if it works, but seems a bit ridiculous since it is suppose to be a GUI and all. 

 

I will navigate to all my IP folders and chmod the appropriate files and come back here at some point to let you know. Pretty silly. 

Andrew
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andrewjcart
Explorer
Explorer
14,962 Views
Registered: ‎09-16-2010

Changing the IP files  (.xci and .xml) permissions to read-only (from Cygwin) resolves the issue. 

Andrew
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