[ISE14.2]when i instantiate the fifo ipcore with .xco file, there is always a error called "Illegal redeclaration of XXX"

[retni]

The 'XXX' in title means the ipcore name.

When i remove the .xco file and add the .v and .ngc file to my project, the problem was resolved.

I wanna know why this happen?

I always used the .xco file to instanstiate the ipcore in the former release of the ISE....

[howardp]

When you add the .xco file, you are adding an IP core sub project.

Project Navigator automatically accesses files from the core subproject during the various flows according to project settings, the flow that is being run, and the designation of files in the IP cor esubproject.

Typically, a redeclaration error is caused when a second declarationof a module is inadvertently sent to synthesis.

Recently, we've seen an issue with a few IP (including the Fifo) where a XXX_synth.v file was incorrectly generated and added for synthesis and simulation flows.  If the file is deleted, the flows complete successfully.

I can say this is the problem you are seeing for sure with the information given but, it would be my first guess.  The error message should give more information about which files are involved. 

[retni]

thanks for your reply!

i copy the error message to below:

ERROR:HDLCompilers:27 - "ipcore_dir/fifo_dsp_write.v" line 39 Illegal redeclaration of 'fifo_dsp_write'

 if i cancel the .v file, i can synthesis the project, but i can't simulate it!

so my solution is remove the .xco file and add the .v file and the .ngc file.

but the .xco file is useless in this way..

[dzz870529]

I have met the same problem.The memory Ipcore always display the illegal redeclaration.

[dzz870529]

I use the ISE14.1 to test the block ram ipcore only ,there is no erro. So I think this is the bug or setting problems of the ISE14.2

[retni]

i never met this problem in other version of ISE...

this is a troublesome bug....wish there is a bugfix soon.

[davidbowman]

Same problem here.

I love upgrading to new versions of ISE only to find stuff that's been working for ages breaks.

[eteam00]

I love upgrading to new versions of ISE only to find stuff that's been working for ages breaks.

It is very risky to change (or update) design tools in the middle of a design project.  This includes schematic capture, synthesis, simulation, place/route, and operating system.  Wait until your project is released and completely, absolutely archived.

New bugs, as well as bug fixes and new features, are to be expected with new tools releases.  There is logic in never using the latest release of anything, instead using a release  for which bugs and workarounds have already been documented and published.

-- Bob Elkind

[cimasys]

I also have a problem with .xco instantiations.  At the bottom of the screen is an example using an .xco file to instantiate a coregen module.  It references a DDS in lieu of the FIR that it should be using.  I have gotten used to instantiating .v + .ngc instead of .xco.  And yes, it does work when I manually instantiate the .v+.ngc FIR module so it has no issues with ports or anything else.  This is with PlanAhead 14.4