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Visitor
Visitor
5,484 Views
Registered: ‎06-24-2009

Inlcude file function

Hi,

 

I was wondering if ISE and VHDL support a function.

 

I would like the main file but to have different logic in a seperate file as it can be many thousands of lines and I dont need to load it into the ise editor..

 

such as

 


    process(Clock, Reset)
    begin
        {$include c:\testcode.vhd}
    end process;

 

thanks for your help

Justin

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Historian
Historian
5,474 Views
Registered: ‎02-25-2008


@justronics wrote:

Hi,

 

I was wondering if ISE and VHDL support a function.

 

I would like the main file but to have different logic in a seperate file as it can be many thousands of lines and I dont need to load it into the ise editor..

 

such as

 


    process(Clock, Reset)
    begin
        {$include c:\testcode.vhd}
    end process;

 

thanks for your help

Justin


VHDL does not include an include function call or macro or anything like that.

 

Might I suggest making the code you want to "include" into an entity and instantiating that entity in the usual way?

----------------------------Yes, I do this for a living.
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Teacher
Teacher
5,466 Views
Registered: ‎08-14-2007

Hi,

besides the already mentioned instatiation there are also packages.

 

The VHDL and ADA package concept is far more flexible and reliable than includes can be.

 

In a package you can put type definitions, declarations, functions and procedures.

(Actually the libraries you always include are packages too, providing you with very powerful functions like type conversions etc.)

 

Have a nice synthesis

  Eilert

 

 

 

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