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7,464 Views
Registered: ‎07-27-2015

Interconnect DECERR

Hi,

 

I have PCIe bridge that has data bus 256bit connected to BRAM ctrl slave which has 128 bit bus width using interconnect.
Im trying to send a read transaction from master to slave and read addres 5000_0000.
(Slave is mapped to  address space 5000_0000-5000_3FFF).

The transaction in master side is with ARSIZE=3 (meaning using only 64 bit) butI see the interconnect is returning
RRESP=3 meaning decode ERROR.
Can you help me understand why?

 

Thank you!

 

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5 Replies
Xilinx Employee
Xilinx Employee
7,454 Views
Registered: ‎08-02-2011

Re: Interconnect DECERR

For slave errors, I always start by checking the addressing. What address is being requested of the interconnect (i.e. capture the whole request with an ILA)? Does  that address map to the slave you expect in Vivado address editor?

www.xilinx.com
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7,444 Views
Registered: ‎07-27-2015

Re: Interconnect DECERR

Yes I captured all request in ILA, I see the Master request address 'h5000_0000.

That address is declared in the address editor in the Vivado.
Attached address editor snapshot and chip scope waves.

Thank you!

lital_int_rd.PNG
address_editor.PNG
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Highlighted
7,430 Views
Registered: ‎07-27-2015

Re: Interconnect DECERR

It seems RRESP is going '3' even before the read request but this is for sure the first read in this run!
Can you help me understand the reason for that?

 

Thank you so much!

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7,405 Views
Registered: ‎07-27-2015

Re: Interconnect DECERR

Hello!

I realy need your help!
It seems interconnect is returning RRESp=3 (DECERR) after this read and I cant undertstand why!
I attached the update snapshot.
I will really appriciate your help..

thank you

rresp_decerr.PNG
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7,385 Views
Registered: ‎07-27-2015

Re: Interconnect DECERR

Can you please help ?

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