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Contributor
Contributor
375 Views
Registered: ‎07-26-2018

Internal Exception Error vivado 2018.2

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Hi, I created a block design then created hdl  wrapper. I try to add my rtl modul this hdl wrapper(hdmi_wrapper). The reason why that i'm doing is that in my rtl design has custom type and the block diagram does not accept custom type port definition therefore i am mapping manuel "prot map".when İ try to adding my rtl design(top.vhd) in vhdl wrapper file, vivado give me this error.

blogdiagramhdmi.JPG

vivadoerror.JPG

 

#--------------------------------------------------------------------------
# Xilinx Vivado v2018.2 (64-bit)
# SW Build: 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build: 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Current time: Wed Apr 17 16:03:28 EEST 2019
# Process ID: 2880
# User: palto
# OS: Windows 10
#
# This report is an indication that an internal application error occurred.
# This information is useful for debugging. Please open a case with Xilinx.
# Technical Support with this file and a testcase attached.
#--------------------------------------------------------------------------
java.lang.NullPointerException
	at ui.views.V.a.Z.e(SourceFile:2612)
	at ui.views.V.a.Z.guy(SourceFile:1754)
	at ui.views.V.a.Z.inspectCode(SourceFile:3550)
	at com.jidesoft.editor.CodeEditor.documentChanged(Unknown Source)
	at com.jidesoft.editor.CodeEditor$q_.insertUpdate(Unknown Source)
	at javax.swing.text.AbstractDocument.fireInsertUpdate(AbstractDocument.java:201)
	at com.jidesoft.editor.SyntaxDocument.fireInsertUpdate(Unknown Source)
	at javax.swing.text.AbstractDocument.handleInsertString(AbstractDocument.java:748)
	at javax.swing.text.AbstractDocument.insertString(AbstractDocument.java:707)
	at javax.swing.text.PlainDocument.insertString(PlainDocument.java:130)
	at com.jidesoft.editor.b.insertStringAtCaret(Unknown Source)
	at com.jidesoft.editor.CodeEditor.d(Unknown Source)
	at com.jidesoft.editor.CodeEditor.c(Unknown Source)
	at com.jidesoft.editor.CodeEditor.insertChar(Unknown Source)
	at ui.views.V.a.Z.insertChar(SourceFile:3401)
	at com.jidesoft.editor.action.InputHandler$bb_.actionPerformed(Unknown Source)
	at com.jidesoft.editor.action.InputHandler.executeAction(Unknown Source)
	at com.jidesoft.editor.action.InputHandler.keyTyped(Unknown Source)
	at com.jidesoft.editor.CodeEditor.processKeyEvent(Unknown Source)
	at ui.views.V.a.Z.processKeyEvent(SourceFile:2668)
	at java.awt.Component.processEvent(Component.java:6310)
	at java.awt.Container.processEvent(Container.java:2236)
	at ui.views.V.a.Z.processEvent(SourceFile:2674)
	at java.awt.Component.dispatchEventImpl(Component.java:4889)
	at java.awt.Container.dispatchEventImpl(Container.java:2294)
	at java.awt.Component.dispatchEvent(Component.java:4711)
	at java.awt.KeyboardFocusManager.redispatchEvent(KeyboardFocusManager.java:1954)
	at java.awt.DefaultKeyboardFocusManager.dispatchKeyEvent(DefaultKeyboardFocusManager.java:806)
	at java.awt.DefaultKeyboardFocusManager.preDispatchKeyEvent(DefaultKeyboardFocusManager.java:1074)
	at java.awt.DefaultKeyboardFocusManager.typeAheadAssertions(DefaultKeyboardFocusManager.java:945)
	at java.awt.DefaultKeyboardFocusManager.dispatchEvent(DefaultKeyboardFocusManager.java:771)
	at java.awt.Component.dispatchEventImpl(Component.java:4760)
	at java.awt.Container.dispatchEventImpl(Container.java:2294)
	at java.awt.Window.dispatchEventImpl(Window.java:2746)
	at java.awt.Component.dispatchEvent(Component.java:4711)
	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:758)
	at java.awt.EventQueue.access$500(EventQueue.java:97)
	at java.awt.EventQueue$3.run(EventQueue.java:709)
	at java.awt.EventQueue$3.run(EventQueue.java:703)
	at java.security.AccessController.doPrivileged(Native Method)
	at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:80)
	at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:90)
	at java.awt.EventQueue$4.run(EventQueue.java:731)
	at java.awt.EventQueue$4.run(EventQueue.java:729)
	at java.security.AccessController.doPrivileged(Native Method)
	at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:80)
	at java.awt.EventQueue.dispatchEvent(EventQueue.java:728)
	at ui.frmwork.b.d.dispatchEvent(SourceFile:76)
	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:201)
	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:116)
	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:105)
	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:101)
	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:93)
	at java.awt.EventDispatchThread.run(EventDispatchThread.java:82)
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
--Date        : Wed Apr 17 14:43:00 2019
--Host        : DESKTOP-G88BE3T running 64-bit major release  (build 9200)
--Command     : generate_target hdmi_wrapper.bd
--Design      : hdmi_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_wrapper is
  port (
    DDC_scl_io : inout STD_LOGIC;
    DDC_sda_io : inout STD_LOGIC;
    PixelClk_0 : out STD_LOGIC;
    PixelClk_1 : in STD_LOGIC;
    TMDS_1_clk_n : out STD_LOGIC;
    TMDS_1_clk_p : out STD_LOGIC;
    TMDS_1_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_1_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_clk_n : in STD_LOGIC;
    TMDS_clk_p : in STD_LOGIC;
    TMDS_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 );
    aRst_0 : in STD_LOGIC;
    aRst_1 : in STD_LOGIC;
    hdmi_in_hpd : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_0 : in STD_LOGIC;
    sys_clock : in STD_LOGIC;
    vid_pData_0 : out STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pData_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pHSync_0 : out STD_LOGIC;
    vid_pHSync_1 : in STD_LOGIC;
    vid_pVDE_0 : out STD_LOGIC;
    vid_pVDE_1 : in STD_LOGIC;
    vid_pVSync_0 : out STD_LOGIC;
    vid_pVSync_1 : in STD_LOGIC
  );
end hdmi_wrapper;

architecture STRUCTURE of hdmi_wrapper is
  component hdmi is
  port (
    DDC_scl_i : in STD_LOGIC;
    DDC_scl_o : out STD_LOGIC;
    DDC_scl_t : out STD_LOGIC;
    DDC_sda_i : in STD_LOGIC;
    DDC_sda_o : out STD_LOGIC;
    DDC_sda_t : out STD_LOGIC;
    TMDS_clk_p : in STD_LOGIC;
    TMDS_clk_n : in STD_LOGIC;
    TMDS_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_1_clk_p : out STD_LOGIC;
    TMDS_1_clk_n : out STD_LOGIC;
    TMDS_1_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_1_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    aRst_0 : in STD_LOGIC;
    sys_clock : in STD_LOGIC;
    hdmi_in_hpd : out STD_LOGIC_VECTOR ( 0 to 0 );
    vid_pData_0 : out STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pHSync_0 : out STD_LOGIC;
    vid_pVSync_0 : out STD_LOGIC;
    vid_pVDE_0 : out STD_LOGIC;
    PixelClk_0 : out STD_LOGIC;
    aRst_1 : in STD_LOGIC;
    reset_0 : in STD_LOGIC;
    vid_pData_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pHSync_1 : in STD_LOGIC;
    vid_pVSync_1 : in STD_LOGIC;
    vid_pVDE_1 : in STD_LOGIC;
    PixelClk_1 : in STD_LOGIC
  );
  end component hdmi;
  component IOBUF is
  port (
    I : in STD_LOGIC;
    O : out STD_LOGIC;
    T : in STD_LOGIC;
    IO : inout STD_LOGIC
  );
  end component IOBUF;
  signal DDC_scl_i : STD_LOGIC;
  signal DDC_scl_o : STD_LOGIC;
  signal DDC_scl_t : STD_LOGIC;
  signal DDC_sda_i : STD_LOGIC;
  signal DDC_sda_o : STD_LOGIC;
  signal DDC_sda_t : STD_LOGIC;
begin
DDC_scl_iobuf: component IOBUF
     port map (
      I => DDC_scl_o,
      IO => DDC_scl_io,
      O => DDC_scl_i,
      T => DDC_scl_t
    );
DDC_sda_iobuf: component IOBUF
     port map (
      I => DDC_sda_o,
      IO => DDC_sda_io,
      O => DDC_sda_i,
      T => DDC_sda_t
    );
hdmi_i: component hdmi
     port map (
      DDC_scl_i => DDC_scl_i,
      DDC_scl_o => DDC_scl_o,
      DDC_scl_t => DDC_scl_t,
      DDC_sda_i => DDC_sda_i,
      DDC_sda_o => DDC_sda_o,
      DDC_sda_t => DDC_sda_t,
      PixelClk_0 => PixelClk_0,
      PixelClk_1 => PixelClk_1,
      TMDS_1_clk_n => TMDS_1_clk_n,
      TMDS_1_clk_p => TMDS_1_clk_p,
      TMDS_1_data_n(2 downto 0) => TMDS_1_data_n(2 downto 0),
      TMDS_1_data_p(2 downto 0) => TMDS_1_data_p(2 downto 0),
      TMDS_clk_n => TMDS_clk_n,
      TMDS_clk_p => TMDS_clk_p,
      TMDS_data_n(2 downto 0) => TMDS_data_n(2 downto 0),
      TMDS_data_p(2 downto 0) => TMDS_data_p(2 downto 0),
      aRst_0 => aRst_0,
      aRst_1 => aRst_1,
      hdmi_in_hpd(0) => hdmi_in_hpd(0),
      reset_0 => reset_0,
      sys_clock => sys_clock,
      vid_pData_0(23 downto 0) => vid_pData_0(23 downto 0),
      vid_pData_1(23 downto 0) => vid_pData_1(23 downto 0),
      vid_pHSync_0 => vid_pHSync_0,
      vid_pHSync_1 => vid_pHSync_1,
      vid_pVDE_0 => vid_pVDE_0,
      vid_pVDE_1 => vid_pVDE_1,
      vid_pVSync_0 => vid_pVSync_0,
      vid_pVSync_1 => vid_pVSync_1
    );
  
end STRUCTURE;
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1 Solution

Accepted Solutions
Scholar dpaul24
Scholar
351 Views
Registered: ‎08-07-2014

Re: Internal Exception Error vivado 2018.2

Jump to solution

@fpgatr,

I think the BD should have a Wrapper first. Then this custom module of yours should be connected to the Wrapper ports. Consequently put this Wrapper and your custom module inside a top module.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
6 Replies
Contributor
Contributor
362 Views
Registered: ‎07-26-2018

Re: Internal Exception Error vivado 2018.2

Jump to solution

I used the solution in this title but I'm not sure what I'm doing is right.

https://forums.xilinx.com/t5/Design-Entry/Vivado-internal-exception/td-p/376249

This is the situation after "port map". 

Again,  The reason why that i'm doing is that in my rtl design has custom type and the block diagram does not accept custom type port definition.

son hali.JPG

--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
--Date        : Wed Apr 17 14:43:00 2019
--Host        : DESKTOP-G88BE3T running 64-bit major release  (build 9200)
--Command     : generate_target hdmi_wrapper.bd
--Design      : hdmi_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_wrapper is
  port (
    DDC_scl_io : inout STD_LOGIC;
    DDC_sda_io : inout STD_LOGIC;
    PixelClk_0 : out STD_LOGIC;
    PixelClk_1 : in STD_LOGIC;
    TMDS_1_clk_n : out STD_LOGIC;
    TMDS_1_clk_p : out STD_LOGIC;
    TMDS_1_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_1_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_clk_n : in STD_LOGIC;
    TMDS_clk_p : in STD_LOGIC;
    TMDS_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 );
    aRst_0 : in STD_LOGIC;
    aRst_1 : in STD_LOGIC;
    hdmi_in_hpd : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_0 : in STD_LOGIC;
    sys_clock : in STD_LOGIC;
    vid_pData_0 : out STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pData_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pHSync_0 : out STD_LOGIC;
    vid_pHSync_1 : in STD_LOGIC;
    vid_pVDE_0 : out STD_LOGIC;
    vid_pVDE_1 : in STD_LOGIC;
    vid_pVSync_0 : out STD_LOGIC;
    vid_pVSync_1 : in STD_LOGIC
  );
end hdmi_wrapper;

architecture STRUCTURE of hdmi_wrapper is
  component hdmi is
  port (
    DDC_scl_i : in STD_LOGIC;
    DDC_scl_o : out STD_LOGIC;
    DDC_scl_t : out STD_LOGIC;
    DDC_sda_i : in STD_LOGIC;
    DDC_sda_o : out STD_LOGIC;
    DDC_sda_t : out STD_LOGIC;
    TMDS_clk_p : in STD_LOGIC;
    TMDS_clk_n : in STD_LOGIC;
    TMDS_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_1_clk_p : out STD_LOGIC;
    TMDS_1_clk_n : out STD_LOGIC;
    TMDS_1_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_1_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    aRst_0 : in STD_LOGIC;
    sys_clock : in STD_LOGIC;
    hdmi_in_hpd : out STD_LOGIC_VECTOR ( 0 to 0 );
    vid_pData_0 : out STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pHSync_0 : out STD_LOGIC;
    vid_pVSync_0 : out STD_LOGIC;
    vid_pVDE_0 : out STD_LOGIC;
    PixelClk_0 : out STD_LOGIC;
    aRst_1 : in STD_LOGIC;
    reset_0 : in STD_LOGIC;
    vid_pData_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
    vid_pHSync_1 : in STD_LOGIC;
    vid_pVSync_1 : in STD_LOGIC;
    vid_pVDE_1 : in STD_LOGIC;
    PixelClk_1 : in STD_LOGIC
  );
  end component hdmi;
  component IOBUF is
  port (
    I : in STD_LOGIC;
    O : out STD_LOGIC;
    T : in STD_LOGIC;
    IO : inout STD_LOGIC
  );
  end component IOBUF;
  signal DDC_scl_i : STD_LOGIC;
  signal DDC_scl_o : STD_LOGIC;
  signal DDC_scl_t : STD_LOGIC;
  signal DDC_sda_i : STD_LOGIC;
  signal DDC_sda_o : STD_LOGIC;
  signal DDC_sda_t : STD_LOGIC;
  
  
      
  component top is
  Port (  
      clk           : in std_logic;
      rst           : in std_logic;
      hdmi_i_active : in std_logic;
      hdmi_o_active : out std_logic;                    
      datain        : in std_logic_vector(23 downto 0);
      dataout       : out std_logic_vector(23 downto 0)
  );
  end component;   
  
  signal  hdmi_o_active : std_logic;
  signal PixelClk_0_0 : std_logic;
  signal vid_pVDE_0_0 : std_logic;
  signal vid_pData_0_0 : std_logic_vector(23 downto 0);
  signal vid_pData_1_1 : std_logic_vector(23 downto 0);
  
begin
DDC_scl_iobuf: component IOBUF
     port map (
      I => DDC_scl_o,
      IO => DDC_scl_io,
      O => DDC_scl_i,
      T => DDC_scl_t
    );
DDC_sda_iobuf: component IOBUF
     port map (
      I => DDC_sda_o,
      IO => DDC_sda_io,
      O => DDC_sda_i,
      T => DDC_sda_t
    );
hdmi_i: component hdmi
     port map (
      DDC_scl_i => DDC_scl_i,
      DDC_scl_o => DDC_scl_o,
      DDC_scl_t => DDC_scl_t,
      DDC_sda_i => DDC_sda_i,
      DDC_sda_o => DDC_sda_o,
      DDC_sda_t => DDC_sda_t,
      PixelClk_0 => PixelClk_0_0,
      PixelClk_1 => PixelClk_0_0,
      TMDS_1_clk_n => TMDS_1_clk_n,
      TMDS_1_clk_p => TMDS_1_clk_p,
      TMDS_1_data_n(2 downto 0) => TMDS_1_data_n(2 downto 0),
      TMDS_1_data_p(2 downto 0) => TMDS_1_data_p(2 downto 0),
      TMDS_clk_n => TMDS_clk_n,
      TMDS_clk_p => TMDS_clk_p,
      TMDS_data_n(2 downto 0) => TMDS_data_n(2 downto 0),
      TMDS_data_p(2 downto 0) => TMDS_data_p(2 downto 0),
      aRst_0 => reset_0,
      aRst_1 => reset_0,
      hdmi_in_hpd(0) => hdmi_in_hpd(0),
      reset_0 => reset_0,
      sys_clock => sys_clock,
      vid_pData_0(23 downto 0) => vid_pData_0(23 downto 0),
      vid_pData_1(23 downto 0) => vid_pData_1(23 downto 0),
      vid_pHSync_0 => vid_pHSync_0,
      vid_pHSync_1 => vid_pHSync_1,
      vid_pVDE_0 => vid_pVDE_0_0,
      vid_pVDE_1 => vid_pVDE_1,
      vid_pVSync_0 => vid_pVSync_0,
      vid_pVSync_1 => vid_pVSync_1
    );
    
    t : top port map(clk=>PixelClk_0_0, rst=>reset_0, hdmi_i_active=>vid_pVDE_0_0, hdmi_o_active=>hdmi_o_active, datain=>vid_pData_0_0 , dataout=>vid_pData_1_1);
    
end STRUCTURE;
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Scholar dpaul24
Scholar
352 Views
Registered: ‎08-07-2014

Re: Internal Exception Error vivado 2018.2

Jump to solution

@fpgatr,

I think the BD should have a Wrapper first. Then this custom module of yours should be connected to the Wrapper ports. Consequently put this Wrapper and your custom module inside a top module.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
Contributor
Contributor
340 Views
Registered: ‎07-26-2018

Re: Internal Exception Error vivado 2018.2

Jump to solution

@dpaul24 

My rtl design should be between two hdmi module so this may not be.

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Scholar dpaul24
Scholar
309 Views
Registered: ‎08-07-2014

Re: Internal Exception Error vivado 2018.2

Jump to solution

@fpgatr,

My rtl design should be between two hdmi module so this may not be.

To answer this, I have to understand what you are trying to do.

I see you are bring in HDMI signals, using two IP blocks and then output the HDMI signal again. What is your custom block doing and where do you want to connect it?

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
Highlighted
Contributor
Contributor
293 Views
Registered: ‎07-26-2018

Re: Internal Exception Error vivado 2018.2

Jump to solution

@dpaul24 

I think the BD should have a Wrapper first. Then this custom module of yours should be connected to the Wrapper ports. Consequently put this Wrapper and your custom module inside a top module.

what you're saying is true. This is my inexperience. thanks.

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Scholar dpaul24
Scholar
240 Views
Registered: ‎08-07-2014

Re: Internal Exception Error vivado 2018.2

Jump to solution

@fpgatr,

You are welcome!

This is my inexperience. thanks.

That is why, they say always read the documentation! :-)

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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